Method and apparatus for timing and event processing in wireless systems
A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.
1. A method for generating a calibrated clock, comprising:
receiving a free-running fast clock;
receiving a free-running slow clock;
modifying the free-running slow clock with a fractional-N clock divider which removes clock cycles from the free-running slow clock in response to specified fraction and modulus values, and information obtained by comparing the free-running slow clock to the free-running fast clock, to provide a calibrated slow clock having a specified frequency relationship to the slow clock;
providing a phase compensation value that represents a phase error for each clock cycle of the calibrated slow clock, wherein the phase compensation value increases with each slow clock cycle until a clock cycle is removed and then the chase compensation value is decreased accordingly; and
deriving event timing from the calibrated slow clock and the phase compensation value to provide event timing with the accuracy of the free-running fast clock.
2. A method as defined in claim 1 , wherein the step of modifying the free-running slow clock further comprises counting the number of fast clock cycles in a selected number of free-running slow clock cycles and determining a period with which cycles are removed from the free-running slow clock based on the specified frequency relationship and the number of fast clock cycles in the selected number of free-running slow clock cycles.
3. A method for generating a calibrated clock, comprising:
receiving a free-running fast clock;
receiving a free-running slow clock;
specifying a relationship between the fast clock and a calibrated slow clock;
counting the number of fast clock cycles in a selected number of free-running slow clock cycles to provide a comparison value;
removing cycles from the free-running slow clock with a fractional-N clock divider to provide the calibrated slow clock, based on the specified relationship between the fast clock and the calibrated slow clock, the specified relationship including specified fraction and modulus values, and based on the comparison value;
providing a phase compensation signal that represents a phase error for each clock cycle of the calibrated slow clock, wherein the phase compensation value increases with each slow clock cycle until a clock cycle is removed and then the phase compensation value is decreased accordingly; and
deriving event timing from the calibrated slow clock and the phase compensation signal to provide event timing with the accuracy of the free-running fast clock.
4. A method as defined in claim 3 , wherein the step of providing a phase compensation signal comprises providing a number of fast clock cycles that represents the phase error.
5. Apparatus for generating a calibrated clock comprising:
means for receiving a free-running fast clock;
means for receiving a free-running slow clock;
a fractional-N clock divider for modifying the free-running slow clock, the fractional-N clock divider removing clock cycles from the free-running slow clock in response to specified fraction and modulus values, and information obtained from comparing the free-running slow clock to the free-running fast clock, to provide a calibrated slow clock having a specified frequency relationship to the fast clock;
means for providing a phase compensation signal that represents a phase error for each clock cycle of the calibrated slow clock, wherein the phase compensation signal increases with each slow clock cycle until a clock cycle is removed and then the phase compensation signal is decreased accordingly; and
means for deriving event timing from the calibrated slow clock and the phase compensation signal to provide event timing with the accuracy of the free-running fast clock.
6. A method as defined in claim 1 , wherein the calibrated slow clock and the phase compensation value continue to be provided if the free-running fast clock is switched off.
7. A method as defined in claim 3 , wherein the calibrated slow clock and the phase compensation value continue to be provided if the free-running fast clock is switched off.
8. Apparatus as defined in claim 5 , wherein the calibrated slow clock and the phase compensation signal continue to be provided if the free-running fast clock is switched off.