Double-sided thermally enhanced IC chip package

1. An IC chip package comprising:

a substrate having a top and bottom surfaces on which conductive circuit patterns are respectively laid, and an opening extended from the top surface to the bottom surface;

an IC chip having an active side and an inactive side, said chip being received in said opening of said substrate in such a way that said active side of said chip and said top surface of said substrate face to a same direction, said active side of the chip being electrically connected to the conductive circuit pattern on the top surface of said substrate through bonding wires;

a thermally and electrically conductive adhesive layer disposed on said inactive side of said chip and on said bottom surface of said substrate in a completely enclosing way around said opening;

a thermally and electrically conductive planar member having a top and bottom surfaces, said planar member being attached to said thermally and electrically conductive adhesive layer with said top surface thereof;

a dielectric encapsulant encapsulating the opening, the bonding wires, a portion of the active side of the chip to which the bonding wires are connected, and a portion of the top surface of the substrate to which the bonding wires are connected; and

a thermally and electrically conductive encapsulant covered over the dielectric encapsulant, the other portion of the active side of the chip, and the other portion of the top surface of the substrate.

2. The IC chip package of claim 1 , wherein further comprises a plurality of solder balls being electrically connected to the conductive pattern on said bottom surface of said substrate.

3. The IC chip package of claim 1 , wherein the conductive circuit pattern on the top surface of the substrate has a ground end which is covered by the thermally and electrically conductive encapsulant such that the ground end is electrically connected to the thermally and electrically conductive encapsulant.

4. The IC chip package of claim 3 , wherein the conductive circuit pattern on the top surface of the substrate is partially covered by a solder mask layer on which a metal foil is covered.

5. The IC chip package of claim 1 , wherein said thermally and electrically conductive planar member is a copper plate.

6. The IC chip package of claim 1 , wherein said thermally and electrically conductive adhesive layer is a copper paste.

7. The IC chip package of claim 1 , wherein said thermally and electrically conductive encapsulant is made of a copper paste.

8. An IC chip package comprising:

a substrate having a top and bottom surfaces on which conductive circuit patterns are respectively laid, and an opening extended from the top surface to the bottom surface;

a lower IC chip having an active side and an inactive side, said chip being received in said opening of said substrate in such a way that said active side of said chip and said top surface of said substrate face to a same direction, said active side of the chip being electrically connected to the conductive circuit pattern on the top surface of said substrate through bonding wires;

a thermally and electrically conductive adhesive layer disposed on said inactive side of said chip and on said bottom surface of said substrate in a completely enclosing way around said opening;

a thermally and electrically conductive planar member having a top and bottom surfaces, said planar member being attached to said thermally and electrically conductive adhesive layer with said top surface thereof;

a first dielectric encapsulant covered on the active side of the lower IC chip;

an upper IC chip having an active side and an inactive side bonded to said first dielectric encapsulant, said active side of the upper IC chip being electrically connected to the conductive circuit pattern on the top surface of said substrate through another bonding wires;

a second dielectric encapsulant encapsulating the opening, the lower IC chip, the bonding wires, a portion of the active side of the upper IC chip to which the bonding wires are connected, and a portion of the top surface of the substrate to which the bonding wires are connected;

a thermally and electrically conductive encapsulant covered over the second dielectric encapsulant, the other portion of the active side of the upper chip, and the other portion of the top surface of the substrate.

9. The IC chip package of claim 8 further comprising a plurality of solder balls being electrically connected to the conductive pattern on said bottom surface of said substrate.

10. The IC chip package of claim 8 , wherein the conductive circuit pattern on the top surface of the substrate has a ground end which is covered by the thermally and electrically conductive encapsulant such that the ground end is electrically connected to the thermally and electrically conductive encapsulant.

11. The IC chip package of claim 10 , wherein the conductive circuit pattern on the top surface of the substrate is partially covered by a solder mask layer on which a metal foil is covered.

12. The IC chip package of claim 8 , wherein said thermally and electrically conductive planar member is a copper plate.

13. The IC chip package of claim 8 , wherein said thermally and electrically conductive adhesive layer is a copper paste.

14. The IC chip package of claim 8 , wherein said thermally and electrically conductive encapsulant is made of a copper paste.

15. The IC chip package of claim 8 , wherein the first dielectric encapsulant encapsulates the lower IC chip.