Logic array devices having complex macro-cell architecture and methods facilitating use of same
View Patent ↗Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
1. A semiconductor device comprising an array of logic cells and programmable metal, at least some of the logic cells comprising:
at least one prewired gate structure selected from a group consisting of a NAND, a multiplexer, a FLOP, an inverter, an XOR, a NOR, and a look-up table, the at least one gate structure having been fabricated in a first process geometry;
wherein a plurality of input/outputs of the at least one gate structure have been routed in at least two layers of the programmable metal fabricated in a second process geometry.
2. The semiconductor device of claim 1 wherein the first process geometry is smaller than the second process geometry.
3. The semiconductor device of claim 2 wherein the first process geometry corresponds to a 0.18-micron process and the second process geometry corresponds to a 0.25-micron process.
4. The semiconductor device of claim 1 wherein at least some of the logic cells comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
5. The semiconductor device of claim 2 wherein at least some of the logic cells comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
6. The semiconductor device of claim 3 wherein at least some of the logic cells comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
7. The semiconductor device of claim 4 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
8. The semiconductor device of claim 5 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
9. The semiconductor device of claim 6 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
10. A semiconductor device comprising an array of logic cells, the semiconductor device further comprising:
a plurality of input/output tracks, at least one input/output track corresponding to an input for a gate structure in a logic cell of the array of logic cells; and
at least one selectable, in-line inverter disposed to share the at least one input/output track of the plurality of input/output tracks;
wherein each at least one selectable, in-line inverter has been selectively placed in series with the input for the gate structure sharing the input/output track based on programmable via connections.
11. The semiconductor device of claim 10 wherein at least some of the logic cells comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
12. The semiconductor device of claim 10 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
13. The semiconductor device of claim 11 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
14. A semiconductor chip comprising an array of logic cells disposed to receive programmable metal, at least some of the logic cells comprising:
a plurality of gate structures further comprising a plurality of NAND gates, a plurality of multiplexers, a FLOP, and a high-drive inverter; and
random access memory connected to common select and read/write lines;
wherein the plurality of gate structures are pre-wired and a plurality of input/outputs of the plurality of gate structures are available for routing in the programmable metal.
15. A semiconductor chip comprising an array of logic cells, the semiconductor chip further comprising:
a plurality of input/outputs arranged along input/output tracks, at least one input/output corresponding to at least one input/output track connected to an input for a gate structure in a logic cell of the array of logic cells; and
at least one selectable, in-line inverter disposed to share the at least one input/output track of the plurality of input/output tracks;
wherein each at least one selectable, in-line inverter can be selectively placed in series with the input so as to share the at least one input/output track based on programmable via connections.
16. The semiconductor chip of claim 15 , wherein at least some of the logic cells comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
17. The semiconductor chip of claim 15 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
18. The semiconductor chip of claim 16 wherein at least some of the logic cells further comprise random access memory connected to common select and read/write lines.
19. A semiconductor device comprising an array of logic cells and programmable metal, at least some of the logic cells comprising:
a prewired multiplexer (MUX) having two inputs; and
a selectable, in-line inverter that shares an input/output track with one input of the two inputs of the prewired MUX;
wherein the one prewired inverter has been selectively connected to the one input by routing in the programmable metal.
20. A semiconductor device comprising an array of logic cells and programmable metal, at least some of the logic cells comprising:
a prewired multiplexer (MUX) having two inputs; and
one prewired inverter associated with one input of the two inputs of the prewired MUX;
wherein the one prewired inverter has been selectively connected to the one input by routing in the programmable metal, and wherein the prewired MUX and the prewired inverter have been fabricated in a first process geometry and the programmable metal has been fabricated in a second process geometry.
21. A semiconductor device comprising an array of logic cells and programmable metal, at least some of the logic cells comprising:
a prewired multiplexer (MUX) having two inputs;
one prewired inverter associated with one input of the two inputs of the prewired MUX;
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter;
wherein the one prewired inverter has been selectively connected to the one input by routing in the programmable metal.
22. The semiconductor device of claim 19 wherein at least some of the logic cells further comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
23. The semiconductor device of claim 20 wherein at least some of the logic cells further comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
24. A semiconductor chip comprising an array of logic cells disposed to receive programmable metal, at least some of the logic cells comprising:
a prewired multiplexer (MUX) having two inputs; and
a selectable, in-line inverter that shares an input/output track with one input of the two inputs of the prewired MUX;
wherein the one prewired inverter can be selectively connected to the one input by routing in the programmable metal.
25. A semiconductor chip comprising an array of logic cells disposed to receive programmable metal, at least some of the logic cells comprising:
a prewired multiplexer (MUX) having two inputs;
one prewired inverter associated with one input of the two inputs of the prewired MUX;
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter;
wherein the one prewired inverter can be selectively connected to the one input by routing in the programmable metal.
26. The semiconductor chip of claim 24 wherein at least some of the logic cells further comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
27. A method of fabricating logic devices, the method comprising:
fabricating semiconductor chips comprising cells having prewired gate structures up to programmable metal layers in a first process geometry; and
finishing the logic devices at least in part by fabricating at least two programmable metal layers on the semiconductor chips in a second process geometry to interconnect at least some of the prewired gate structures.
28. The method of claim 27 wherein the prewired gate structures further comprises at least one prewired gate structure selected from a group consisting of a NAND, a multiplexer, a FLOP, an inverter, an XOR, a NOR, and a look-up table.
29. The method of claim 28 wherein at least some of the cells further comprise:
a plurality of NAND gates;
a plurality of multiplexers;
a FLOP; and
an high-drive inverter.
30. The method of claim 27 wherein the first process geometry is smaller than the second process geometry.
31. The method of claim 28 wherein the first process geometry is smaller than the second process geometry.
32. The method of claim 29 wherein the first process geometry is smaller than the second process geometry.
33. The method of claim 30 wherein the first process geometry corresponds to a 0.18-micron process and the second process geometry corresponds to a 0.25-micron process.
34. The method of claim 32 wherein the first process geometry corresponds to a 0.18-micron process and the second process geometry corresponds to a 0.25-micron process.
35. The method of claim 32 wherein the first process geometry corresponds to a 0.18-micron process and the second process geometry corresponds to a 0.25-micron process.