IP Library Assignment 037885/0344
Patent Assignment
Reel/Frame 037885/0344

Security Interest

Recorded: 2016-03-03 Pages: 5
Assignor
TRIAD SEMICONDUCTOR, INC.
Executed: 2016-03-02
Assignee
PARTNERS FOR GROWTH IV, L.P.
1660 TIBURON BLVD, SUITE D, TIBURON, CALIFORNIA, 94920
Covered Properties (14)
Distributed Ram in a Logic Array
Patent: 6,693,454 →
Application: 10/150,685 →
Publication: US 2003/0214322
Cell Architecture to Reduce Customization in a Semiconductor Device
Patent: 6,580,289 →
Application: 10/164,455 →
Publication: US 2002/0186045
Logic Array Devices Having Complex Macro-Cell Architecture and Methods Facilitating Use of Same
Patent: 6,873,185 →
Application: 10/234,926 →
Publication: US 2003/0234666
Customization of Structured Asic Devices Using Pre-Process Extraction of Routing Information
Patent: 7,334,208 →
Application: 10/904,411 →
Configurable Integrated Circuit Capacitor Array Using via Mask Layers
Patent: 7,335,966 →
Application: 10/906,527 →
Publication: US 2005/0189614
Via Configurable Architecture for Customization of Analog Circuitry in a Semiconductor Device
Patent: 7,449,371 →
Application: 10/907,456 →
Publication: US 2005/0224982
Logic Array Devices Having Complex Macro-Cell Architecture and Methods Facilitating Use of Same
Patent: 7,248,071 →
Application: 11/023,860 →
Publication: US 2005/0117436
Creating High-Drive Logic Devices from Standard Gates with Minimal Use of Custom Masks
Patent: 7,378,874 →
Application: 11/469,189 →
Publication: US 2008/0054939
Logic Array Devices Having Complex Macro-Cell Architecture and Methods Facilitating Use of Same
Patent: 7,538,580 →
Application: 11/782,616 →
Publication: US 2007/0262789
Configuring Structured Asic Fabric Using Two Non-Adjacent via Layers
Patent: 7,692,309 →
Application: 11/850,791 →
Publication: US 2009/0065813
Configurable Integrated Circuit Capacitor Array Using via Mask Layers
Patent: 7,595,229 →
Application: 11/965,069 →
Publication: US 2008/0108201
Via Configurable Architecture for Customization of Analog Circuitry in a Semiconductor Device
Patent: 7,626,272 →
Application: 12/246,802 →
Publication: US 2009/0032968
Via Configurable Architecture for Customization of Analog Circuitry in a Semiconductor Device
Patent: 7,972,907 →
Application: 12/268,919 →
Publication: US 2009/0061567
Using Selectable in-Line Inverters to Reduce the Number of Inverters in a Semiconductor Design
Patent: 7,930,670 →
Application: 12/432,494 →
Publication: US 2009/0210848
Related Assignments (6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Dec 6, 2012
From: VIASIC, INC.
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 029418/0552 →
Amended and Restated Intellectual Property Security Agreement Mar 16, 2016
From: TRIAD SEMICONDUCTOR, INC.
To: SILICON VALLEY BANK
Reel/Frame 038106/0300 →
Release of Security Interest Jun 30, 2020
From: SILICON VALLEY BANK
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 053087/0492 →
Release of Security Interest Jul 1, 2020
From: SILICON VALLEY BANK
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 053097/0848 →
Security Interest Jul 10, 2020
From: TRIAD SEMICONDUCTOR, INC.
To: CP BF LENDING, LLC
Reel/Frame 053180/0379 →
Release of Security Interest Jul 13, 2020
From: PARTNERS FOR GROWTH IV, L.P.
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 053187/0495 →