IP Library Granted Patent US 7,334,208
Granted Patent B1
US 7,334,208 · App. 10/904,411 · Granted Feb 19, 2008

Customization of structured ASIC devices using pre-process extraction of routing information

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Quick Facts
Patent No.
US 7,334,208
App. No.
10/904,411
Granted
Feb 19, 2008
Kind
B1
Abstract

Customization of structured ASIC devices using pre-process extraction of routing information. Embodiments of the invention can enable a router that can automatically extract a routing graph for a structured ASIC, where the routing graph represents available routing resources on fixed metal layers. The routing graph can be extracted as a pre-process, and saved in a technology file for later use by the router. Additionally, each unique fixed metal wire type found in the layout can be characterized with a master wire definition, including resistance and capacitance estimates. In some embodiments, a global-routing graph can further be extracted from a detailed routing graph.

Claims (56)

1. A method of customizing a structured ASIC, having at least one layer of fixed metal routing wires, for an application through the use of routing information, extracted during a routing pre-process, concerning the fixed metal routing wires in the at least one layer, the method comprising:

examining, as part of an automated routing pre-process, a physical layout for the structured ASIC, including:

automatically determining the fixed metal routing wires in the at least one layer, and

automatically determining configurable portions of the structured ASIC that may be used to connect the fixed metal routing wires, thereby configuring the structured ASIC;

creating nodes based on the examination of the physical layout, each of the nodes representing one or more fixed metal routing wires connected together in the physical layout;

creating edges based on the examination of the physical layout, the edges representing opportunities to use the configurable portions of the ASIC to connect the fixed metal routing wires, as represented by the nodes, in order to create a data structure including at least one routing graph for the structured ASIC; and

routing the structured ASIC using the at least one routing graph to produce a design file for a configured device.

2. The method of claim 1 wherein the step of creating nodes includes both creating nodes representing fixed metal routing wires and creating nodes representing empty space available for routing.

3. The method of claim 2 wherein the edges represent configurable metal traces.

4. The method of claim 2 wherein the edges represent potential locations for vias.

5. The method of claim 4 wherein the creating of the edges further comprises ANDing together metal layers to determine where vias on an intermediate layer can be placed.

6. The method of claim 2 wherein the edges represent both configurable metal traces and potential locations for vias.

7. The method of claim 1 wherein the edges represent configurable metal traces.

8. The method of claim 7 wherein the at least one routing graph is at least one detailed routing graph, and further comprising creating a global routing graph from the at least one detailed routing graph so that the data structure includes at least one detailed routing graph and a global routing graph.

9. The method of claim 1 wherein the edges represent potential locations for vias.

10. The method of claim 9 wherein the creating of the edges further comprises ANDing together metal layers to determine where vias on an intermediate layer can be placed.

11. The method of claim 10 wherein the at least one routing graph is at least one detailed routing graph, and further comprising creating a global routing graph from the at least one detailed routing graph so that the data structure includes at least one detailed routing graph and a global routing graph.

12. The method of claim 1 wherein the edges represent both configurable metal traces and potential locations for vias.

13. The method of claim 12 wherein the at least one routing graph is at least one detailed routing graph, and further comprising creating a global routing graph from the at least one detailed routing graph so that the data structure includes at least one detailed routing graph and a global routing graph.

14. The method of claim 1 wherein the at least one routing graph is at least one detailed routing graph, and further comprising creating a global routing graph from the at least one detailed routing graph so that the data structure includes at least one detailed routing graph and a global routing graph.

15. A computer program product for customizing a structured ASIC, having at least one layer of fixed metal routing wires, for an application through use of routing information, extracted during a routing pre-process, concerning the fixed metal routing wires in the at least one layer, the computer program product including a medium having computer program code embodied therein, the computer program code further comprising:

instructions for examining a physical layout for the structured ASIC, wherein examining includes:

determining the fixed metal routing wires in the at least one layer, and

determining configurable portions of the structured ASIC that may be used to connect the fixed metal routing wires, thereby configuring the structured ASIC;

instructions for creating nodes and edges based on the examination of the physical layout, each of the nodes representing one or more fixed metal routing wires connected together in the physical layout, the edges representing opportunities to use the configurable portions of the ASIC to connect the fixed metal routing wires, as represented by the nodes;

instructions for creating a data structure including a routing graph for the structured ASIC using the nodes and the edges; and

instructions for routing the structured ASIC using the routing graph to produce a design file for a configured device.

16. The computer program product of claim 15 wherein the edges can represent: configurable metal traces, potential locations for vias, or a combination thereof.

17. The computer program product of claim 16 wherein the computer program code further comprises instructions for ANDing together metal layers to determine where vias on an intermediate layer can be placed.

18. The computer program product of claim 17 wherein the instructions for creating the data structure further comprise:

instructions for creating at least one detailed routing graph; and

instructions for creating a global routing graph from the at least one detailed routing graph.

19. The computer program product of claim 16 wherein the instructions for creating the data structure further comprise:

instructions for creating at least one detailed routing graph; and

instructions for creating a global routing graph from the at least one detailed routing graph.

20. The computer program product of claim 15 wherein the computer program code further comprises instructions for ANDing together metal layers to determine where vias on an intermediate layer can be placed.

21. The computer program product of claim 20 wherein the instructions for creating the data structure further comprise:

instructions for creating at least one detailed routing graph; and

instructions for creating a global routing graph from the at least one detailed routing graph.

22. The computer program product of claim 15 wherein the instructions for creating the data structure further comprise:

instructions for creating at least one detailed routing graph; and

instructions for creating a global routing graph from the at least one detailed routing graph.

23. An apparatus for customizing a structured ASIC, having at least one layer of fixed metal routing wires, for an application through the use of routing information, extracted during a routing pre-process, concerning the fixed metal routing wires in the at least one layer, the apparatus comprising:

means for examining a physical layout for the structured ASIC, wherein examining includes:

determining the fixed metal routing wires in the at least one layer, and

determining configurable portions of the structured ASIC that may be used to connect the fixed metal routing wires, thereby configuring the structured ASIC;

means for creating nodes and edges based on the examination of the physical layout, each of the nodes representing one or more fixed metal routing wires connected together in the physical layout, the edges representing opportunities to use the configurable portions of the ASIC to connect the fixed metal routing wires, as represented by the nodes;

means for creating a data structure including a routing graph for the structured ASIC using the nodes and the edges; and

means for routing the structured ASIC using the routing graph to produce a design file for a configured device.

24. The apparatus of claim 23 further comprising means for ANDing together metal layers to determine where vias on an intermediate layer can be placed.

25. The apparatus of claim 24 wherein the means for creating the data structure further comprises:

means for creating at least one detailed routing graph; and

means for creating a global routing graph from the at least one detailed routing graph.

26. The apparatus of claim 23 wherein the means for creating the data structure further comprises:

means for creating at least one detailed routing graph; and

means for creating a global routing graph from the at least one detailed routing graph.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jul 13, 2020
From: PARTNERS FOR GROWTH IV, L.P.
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 053187/0495 →
SECURITY INTEREST Recorded Jul 10, 2020
From: TRIAD SEMICONDUCTOR, INC.
To: CP BF LENDING, LLC
Reel/Frame 053180/0379 →
RELEASE OF SECURITY INTEREST Recorded Jun 30, 2020
From: SILICON VALLEY BANK
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 053087/0492 →
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 16, 2016
From: TRIAD SEMICONDUCTOR, INC.
To: SILICON VALLEY BANK
Reel/Frame 038106/0300 →
SECURITY INTEREST Recorded Mar 3, 2016
From: TRIAD SEMICONDUCTOR, INC.
To: PARTNERS FOR GROWTH IV, L.P.
Reel/Frame 037885/0344 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2012
From: VIASIC, INC.
To: TRIAD SEMICONDUCTOR, INC.
Reel/Frame 029418/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2004
From: COX, WILLIAM D.
To: VIASIC, INC.
Reel/Frame 015345/0459 →