Configurable integrated circuit capacitor array using via mask layers
View Patent ↗A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.
1. A method of forming a combined capacitor device, comprising:
forming an array of individual capacitors divided into capacitor tiles, each capacitor tile comprising at least one capacitor;
forming a first plurality of first metal routing tracks over the at least one capacitor of each capacitor tile, the first metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
connecting said at least one capacitor of each capacitor tile to a first of said first metal routing tracks and also to a second of said first metal routing tracks;
forming a second plurality of second metal routing tracks over the at least one capacitor of each capacitor tile, the second metal routing tracks crossing over the first metal routing tracks of each capacitor tile, the second metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
wherein some of the second metal routing tracks are connected to some of the first metal routing tracks by a plurality of vias, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor; and
wherein at least some of said plurality of vias are formed where the second metal routing tracks cross over the first metal routing tracks.
2. The method according to claim 1 , comprising:
forming said plurality of vias in a single layer.
3. The method according to claim 2 , wherein the single layer is a single programmable via layer.
4. The method according to claim 1 , comprising:
forming at least two spaced apart layers to form the array of individual capacitors;
forming a metal shield layer between the array of capacitors and the first metal routing tracks; and
forming said plurality of vias in a single layer.
5. The method according to claim 4 , comprising:
connecting the metal shield layer to ground.
6. The method according to claim 1 , comprising:
forming at least two spaced apart layers to form the array of individual capacitors.
7. The method according to claim 1 , comprising:
forming a metal shield layer between the array of capacitors and the first metal routing tracks.
8. The method according to claim 7 , comprising:
connecting the metal shield layer to ground.
9. The method according to claim 1 , comprising
forming the first plurality of first metal routing tracks such that each capacitor tile comprises two capacitors arranged in a 1×2 configuration.
10. The method according to claim 1 , comprising:
forming the first metal routing tracks associated with a given capacitor tile to all be parallel to one another and have a first orientation; and
forming the second metal routing tracks associated with a given capacitor tile to all be parallel to one another and have a second orientation, the second orientation being perpendicular to the first orientation.
11. The method according to claim 1 , wherein:
wherein at least some of said plurality of vias are formed where first metal routing tracks associated with one capacitor tile are aligned with second metal routing tracks associated with an adjacent capacitor tile, in a top view of the device.
12. A method of forming a combined capacitor device, comprising:
forming an array of individual capacitors divided into capacitor tiles, each capacitor tile comprising at least one capacitor;
forming a first plurality of first metal routing tracks over the at least one capacitor of each capacitor tile, the first metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
connecting said at least one capacitor of each capacitor tile to a first of said first metal routing tracks and also to a second of said first metal routing tracks;
forming a second plurality of second metal routing tracks over the at least one capacitor of each capacitor tile, the second metal routing tracks crossing over the first metal routing tracks of each capacitor tile, the second metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
wherein some of the second metal routing tracks are connected to some of the first metal routing tracks by a plurality of vias, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor; and
wherein the second plurality of second metal routing tracks are formed such that the first metal routing tracks associated with one capacitor tile are aligned with the second metal routing tracks associated with an adjacent capacitor tile, thereby forming rows of collinear routing tracks, each row comprising at least one first metal routing track and at least one second metal routing track, in a top view of the device.
13. The method according to claim 12 , comprising:
forming at least some of said plurality of vias where the first metal routing tracks associated with one capacitor tile are aligned with the second metal routing tracks associated with an adjacent capacitor tile in said top view, to thereby permit routing of signals throughout the capacitor array.
14. A method of forming a combined capacitor device, comprising:
forming an array of individual capacitors divided into capacitor tiles, each capacitor tile comprising at least one capacitor;
forming a first plurality of first metal routing tracks over the at least one capacitor of each capacitor tile, the first metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
connecting said at least one capacitor of each capacitor tile to a first of said first metal routing tracks and also to a second of said first metal routing tracks;
forming a second plurality of second metal routing tracks over the at least one capacitor of each capacitor tile, the second metal routing tracks crossing over the first metal routing tracks of each capacitor tile, the second metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
wherein some of the second metal routing tracks are connected to some of the first metal routing tracks by a plurality of vias, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor; and
wherein:
each of said individual capacitors comprises a bottom layer spaced apart from a top layer, and
said step of connecting said at least one capacitor of each capacitor tile comprises:
connecting a first contact to the bottom layer and connecting a second contact to the top layer; and then
connecting a first via to said first contact and connecting a second via to said second contact; wherein:
said first via connects to said first of said first metal routing tracks and said second via connects to said second of said first metal routing tracks.
15. A method of forming a combined capacitor device, comprising:
providing an array of individual capacitors divided into capacitor tiles, each capacitor tile comprising:
at least one capacitor;
a first plurality of first metal routing tracks overlaying the at least one capacitor;
a first electrical connection from said at least one capacitor to a first of said first metal routing tracks; and
a second electrical connection from said at least one capacitor to a second of said first metal routing tracks; wherein:
an orientation of the first metal routing tracks is alternated from one capacitor tile to the next; and
forming a second plurality of second metal routing tracks over the at least one capacitor of each capacitor tile, the second metal routing tracks crossing over the first metal routing tracks of each capacitor tile, the second metal routing tracks having an orientation that is alternated from one capacitor tile to the next;
wherein some of the second metal routing tracks are connected to some of the first metal routing tracks by a plurality of vias, such that capacitors belonging to different capacitor tiles are electrically connected to one another by the second metal routing tracks to thereby form a combined capacitor; and
wherein at least some of said plurality of vias are formed where the second metal routing tracks cross over the first metal routing tracks.
16. The method according to claim 15 , comprising:
forming said plurality of vias in a single layer.
17. The method according to claim 16 , wherein the single layer is a single programmable via layer.
18. The method according to claim 15 , wherein:
the first metal routing tracks associated with one capacitor tile are aligned with the second metal routing tracks associated with an adjacent capacitor tile, thereby forming rows of collinear routing tracks, in a top view of the device; and
at least some of said plurality of vias are formed where the first metal routing tracks associated with one capacitor tile are aligned with the second metal routing tracks associated with an adjacent capacitor tile.
19. The method according to claim 15 , wherein:
wherein at least some of said plurality of vias are formed where first metal routing tracks associated with one capacitor tile are aligned with second metal routing tracks associated with an adjacent capacitor tile, in a top view of the device.