Via configurable architecture for customization of analog circuitry in a semiconductor device
View Patent ↗A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
1. A semiconductor device comprising:
a circuit foundation comprising a first plurality of circuit elements;
an interconnect quilt formed over the circuit elements, the interconnect quilt comprising a plurality of sections adjacent to one another, each section having a first layer comprising upper routing tracks and a second layer comprising lower routing tracks with the upper routing tracks crossing over the lower routing tracks at crossover points, the routing tracks in the first and second layers belonging to one section being rotated 90° relative to the routing tracks in the corresponding layers belonging to an adjacent section, and the first plurality of circuit elements being connected to the lower routing tracks; and
a plurality of vias connecting the upper routing tracks to the lower routing tracks at only some of the crossover points in each of a plurality of sections, to thereby interconnect some of said first plurality of circuit elements and form an electrical circuit.
2. The semiconductor device according to claim 1 , wherein:
vias connect routing tracks in one layer of one section that are aligned with routing tracks in a different layer of an adjacent section.
3. The semiconductor device according to claim 1 , wherein:
the vias all belong to a single programmable via layer.
4. The semiconductor device according to claim 1 , further comprising:
a metal shield layer above the plurality of circuit elements and below the interconnect quilt.
5. The semiconductor device according to claim 1 , further comprising:
a metal layer above the layer comprising upper routing tracks.
6. The semiconductor device according to claim 1 , wherein:
said circuit foundation comprises a first plurality of circuit elements of at least three different types; and
said vias connect the upper routing tracks to the lower routing tracks such that the electrical circuit includes circuit elements of at least three different types.
7. The semiconductor device according to claim 6 , wherein:
the circuit elements of at least three different types includes both analog circuit elements and digital circuit elements.
8. The semiconductor device according to claim 1 , wherein:
the first plurality of circuit elements comprises a plurality of analog circuit elements and a plurality of digital circuit elements
the plurality of analog circuit elements are arranged in analog tiles;
the plurality of digital circuit elements are arranged in digital tiles; and
said plurality of vias connect at least some of the analog tiles to least some of the digital tiles to thereby form a mixed signal electrical circuit.
9. The semiconductor device according to claim 1 , comprising:
at least one of a fixed analog section and a clock channel.
10. The semiconductor device according to claim 1 , wherein:
the interconnect quilt forms one or more functional blocks selected from a group consisting of analog functional blocks, digital functional blocks, and combinations thereof.
11. The semiconductor device according to claim 1 , comprising:
at least three metal layers, at least one polysilicon layer, and the at least one via layer to interconnect said plurality of circuit elements.
12. A semiconductor device comprising:
a circuit foundation comprising a first plurality of circuit elements, the circuit foundation having an interconnect quilt over the circuit elements, the interconnect quilt comprising a plurality of sections adjacent to one another, each section having a first layer comprising upper routing tracks and a second layer comprising lower routing tracks with the upper routing tracks crossing over the lower routing tracks at crossover points, the routing tracks in the first and second layers belonging to one section being rotated 90° relative to the routing tracks in the corresponding layers belonging to an adjacent section, and the first plurality of circuit elements being connected to the lower routing tracks; and
a plurality of vias connecting the upper routing tracks to the lower routing tracks at only some of the crossover points in each of a plurality of sections, to thereby interconnect some of said first plurality of circuit elements and form an electrical circuit.
13. A semiconductor device comprising:
a first plurality of circuit elements arranged in tiles;
a first set of lower routing tracks which extend in a first direction over a first circuit element;
a second set of lower routing tracks which extend in a second direction over a second circuit element, the second direction being perpendicular to the first direction;
at least one routing track in said first set of lower metal routing tracks being connected to the first circuit element;
at least one routing track in said second set of lower routing tracks being connected to the second circuit element;
a first set of upper routing tracks extending in said second direction and crossing over the first set of lower routing tracks;
a second set of upper routing tracks extending in said first direction and crossing over the second set of lower routing tracks; and
a plurality of vias in a via layer connecting some of the upper routing tracks to some of the lower routing tracks, such that the first and second circuit elements are electrically connected to one another by upper and lower routing tracks.
14. The semiconductor device according to claim 13 , wherein the via layer is a single programmable via layer.
15. The semiconductor device according to claim 13 , comprising:
an interconnect quilt comprising a plurality of layers disposed to interconnect the plurality of circuit elements.
16. The semiconductor device according to claim 15 , wherein the interconnect quilt imparts configuration to the semiconductor device using at least one of the plurality of layers, the configuration being imparted to form functional blocks.
17. The semiconductor device according to claim 16 , wherein the functional blocks are selected from a group consisting of analog functional blocks, digital functional blocks, and combinations thereof.
18. The semiconductor device according to claim 13 , wherein:
the first plurality of circuit elements comprises a plurality of analog circuit elements and a plurality of digital circuit elements
the plurality of analog circuit elements are arranged in analog tiles;
the plurality of digital circuit elements are arranged in digital tiles; and
said plurality of vias connect at least some of the analog tiles to least some of the digital tiles to thereby form a mixed signal electrical circuit.
19. The semiconductor device according to claim 13 , wherein the tiles comprises analog tiles and digital tiles that form a mixed signal structured array.
20. The semiconductor device according to claim 13 , comprising:
at least one of a fixed analog section and a clock channel.
21. The semiconductor device according to claim 13 , wherein:
the interconnect quilt forms one or more functional blocks selected from a group consisting of analog functional blocks, digital functional blocks, and combinations thereof.
22. The semiconductor device according to claim 13 , comprising:
at least three metal layers, at least one polysilicon layer, and the at least one via layer to interconnect said plurality of circuit elements.