Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions
View Patent ↗A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing the custom video/image enhancement function.
1. A display processor integrated circuit, comprising:
a display processor configured to process video; and
programmable logic integrated with the display processor, the programmable logic comprising an array of macrocells surrounded by a ring of interface cells that are adjacent to the macrocells, wherein the programmable logic is unprogrammed when manufacture of the display processor integrated circuit is completed, and wherein the programmable logic is programmable to implement at least one of multiple video enhancement algorithms configured to enhance the video when the display processor integrated circuit is implemented after manufacture in a device configured to display the video.
2. The display processor integrated circuit of claim 1 , wherein the multiple video enhancement algorithms include at least one of a peaking algorithm, a brightness enhancing algorithm, a sharpness enhancing algorithm, an upscaling algorithm, a downscaling algorithm, a 2:2 pulldown algorithm, a 3:2 pulldown algorithm, or a VBI information extracting algorithm.
3. The display processor integrated circuit of claim 1 , wherein the display processor integrated circuit is configured to:
receive the video from an analog-to-digital converter; and
output processed and enhanced video to a display driver including at least one of a CRT driver, an LCD driver, or a plasma display driver.
4. The display processor integrated circuit of claim 1 , wherein the device configured to display the video is an HDTV, the display processor is further configured to process high-definition television video in the HDTV, and wherein the programmable logic is further programmable to enhance the high-definition television video.
5. The display processor integrated circuit of claim 1 , wherein the device configured to display the video is a digitally-enhanced television, the display processor integrated circuit is part of the digitally-enhanced television, and wherein the digitally-enhanced television receives the video as at least one of an NTSC signal or a PAL signal.
6. The display processor integrated circuit of claim 1 , wherein the programmable logic comprises at least one of an antifuse-based programmable logic core or a Flash-based programmable logic core.
7. The display processor integrated circuit of claim 1 , wherein the programmable logic comprises a dual-port SRAM memory.
8. The display processor integrated circuit of claim 1 , wherein the programmable logic comprises a configurable SRAM memory block having a configurable width.
9. The display processor integrated circuit of claim 1 , wherein the display processor comprises a memory controller configured to interface with an external memory coupled to the programmable logic.
10. The display processor integrated circuit of claim 1 , wherein the programmable logic comprises logic functionally equivalent to approximately at least 50,000 gates.
11. The display processor integrated circuit of claim 1 , wherein the programmable logic is programmable by customizing only one mask of a multi-mask process used to fabricate the display processor integrated circuit.
12. The display processor integrated circuit of claim 1 , wherein each of the macrocells comprises a dual-port SRAM memory.
13. An integrated circuit, comprising:
a display processor configured to process digital images; and
programmable logic integrated with the display processor, the programmable logic comprising an array of macrocells surrounded by a ring of interface cells that are adjacent to the macrocells, wherein the programmable logic is unprogrammed when manufacture of the integrated circuit is completed, and wherein the programmable logic is programmable to implement at least one of multiple image enhancement algorithms configured to enhance the digital images when the integrated circuit is implemented after manufacture in a device configured to at least one of process or display the digital images.
14. The integrated circuit of claim 13 , wherein the multiple image enhancement algorithms include at least one of a skin tone detection algorithm, a color correction algorithm, a gamma correction algorithm, an edge enhancement algorithm, or an NTSC/PAL encoder.
15. The integrated circuit of claim 13 , wherein the programmable logic comprises at least one of an antifuse-based programmable logic core or a Flash-based programmable logic core.
16. The integrated circuit of claim 13 , wherein the programmable logic comprises a dual-port SRAM memory.
17. The integrated circuit of claim 13 , wherein the programmable logic comprises a configurable SRAM memory block having a configurable width.
18. The integrated circuit of claim 13 , wherein the display processor comprises a memory controller configured to interface with an external memory coupled to the programmable logic.
19. The integrated circuit of claim 13 , wherein the programmable logic is programmable by customizing only one mask of a multi-mask process used to fabricate the integrated circuit.