Method and apparatus for improving testability of I/O driver/receivers
View Patent ↗An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.
1. A method for testing functionality of I/O driver/receivers comprising:
a) connecting a first pad of a first I/O driver/receiver to a second pad of a second I/O driver/receiver;
b) generating a first bit pattern at an input of a driver contained in said first I/O driver/receiver;
c) driving said first bit pattern through said driver of said first I/O driver/receiver to said first pad;
d) driving said first bit pattern to said second pad and through a receiver in said second I/O driver/receiver;
e) comparing said first bit pattern driven through said receiver in said second I/O driver/receiver with a generated second bit pattern identical to said first bit pattern.
2. The method as in claim 1 wherein said first and second bit patterns are generated by a bit pattern generator.
3. The method as in claim 1 wherein said first and said second bit patterns are compared comprising:
a) directing said first bit pattern driven through said receiver in said second I/O driver/receiver into a first clocked register;
b) directing said second bit pattern into a second clocked register;
c) directing output of said first clocked register into a first input of a comparator;
d) directing output of said second clocked register into a second input of a comparator.
4. The method as in claim 3 wherein said comparator is an exclusive OR gate.
5. The method as in claim 3 wherein said comparator is an exclusive NOR gate.