Fin thyristor-based semiconductor device
View Patent ↗A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device. The gate of the pass device is further adapted to switch the pass device between a blocking state and a conducting state via the capacitive coupling and form a conductive path between the source/drain regions. A control port is capacitively coupled to the base region of the end portion of the thyristor that is coupled to the source/drain region of the pass gate and is adapted to facilitate switching of the thyristor between blocking and conducting states.
1. A semiconductor device comprising:
a fin having a top portion and a side portion and extending over a semiconductor substrate and further including two side wall portions extending from the substrate and the top portion between the two side wall portions and wherein the fin is a thin silicon fin having a width between the two side wall portions of between about 5 nanometers and 15 nanometers;
a pass device comprising a channel between source/drain regions, the fin including at least a portion of the channel, the pass device further comprising a gate facing and capacitively coupled to a side portion of the fin that includes the channel and facing both of the side wall portions of the portion of the fin that includes the channel, the gate being adapted to switch the channel between a blocking state and a conducting state for passing current between the source/drain regions in response to a voltage applied thereto;
a thyristor having anode and cathode end portions, each end portion including an emitter region and an adjacent base region, the base regions being coupled between the emitter regions, one of the emitter regions being coupled to one of the source/drain regions of the pass device; and
a control port capacitively coupled to one of the base regions and adapted to facilitate switching of the thyristor between blocking and conducting states.
2. The semiconductor device of claim 1 , further comprising a gate dielectric between the gate and the channel, wherein the gate is capacitively coupled to the channel via a gate dielectric.
3. The semiconductor device of claim 1 , wherein the fin includes at least one of the source/drain regions.
4. The semiconductor device of claim 3 , further comprising a contact region over the at least one of the source/drain regions in the fin, the contact region extending over a portion of the fin and over a portion of the substrate not covered by the fin.
5. The semiconductor device of claim 1 , wherein the fin includes the one of the base regions to which the control port is capacitively coupled.
6. The semiconductor device of claim 5 , wherein the control port is formed around the fin portion.
7. The semiconductor device of claim 1 , wherein the thyristor and the pass device comprise a memory cell adapted for read and write access for storage and retrieval of data.
8. The semiconductor device of claim 7 , wherein the memory cell is part of a memory having a plurality of memory cells arranged in an array and further including a plurality of the thyristors and the pass devices, each of the plurality of the thyristors and pass devices being configured and arranged to provide read and write memory for a corresponding one of the plurality of memory cells.
9. The semiconductor device of claim 1 , wherein the thyristor is a thin capacitively coupled thyristor.
10. The semiconductor device of claim 1 , further comprising an insulator layer, the fin, pass device, thyristor and control port being over the insulator layer, the insulator layer being part of a silicon on insulator (SOI) structure.