Accuracy of timing analysis using region-based voltage drop budgets
View Patent ↗A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.
1. A method for verifying that an integrated circuit meets predefined timing requirements, comprising:
partitioning at least a portion of the integrated circuit into at least one voltage drop region, wherein the at least one voltage drop region inputs a supply voltage determined by a region-based voltage drop budget;
characterizing a time delay for a logic path segment in the at least one voltage drop region using the supply voltage inputted by the at least one voltage drop region; and
determining a critical path for the at least one voltage drop region using the time delay of the logic path segment.
2. The method of claim 1 , further comprising redesigning the critical path to meet the predefined timing requirements.
3. The method of claim 1 , wherein characterizing the time delay of the logic path segment comprises:
determining a set of logic components included in the logic path segment;
computing a time delay for each type of logic component using the supply voltage inputted by the at least one voltage drop region; and
summing the time delays of the set of logic components.
4. The method of claim 1 , wherein the critical path is a min-time path.
5. The method of claim 1 , wherein the critical path is a max-time path.
6. The method of claim 1 , wherein the partitioning the at least a portion of the integrated circuit comprises:
determining a voltage drop criteria for the at least a portion of the integrated circuit;
analyzing the at least a portion of the integrated circuit for worst-case voltage drop data using the voltage drop criteria;
partitioning the at least a portion of the integrated circuit into another at least one voltage drop region based on the worst-case voltage drop data, wherein the another at least one voltage drop region is assigned a region-based voltage drop budget based on a worst-case voltage drop seen by the another at least one voltage drop region.
7. A method for verifying that an integrated circuit meets predefined timing requirements, comprising:
determining at least one voltage drop region for the integrated circuit;
determining a supply voltage for the at least one voltage drop region;
determining a critical path disposed within the at least one voltage drop region using the supply voltage; and
configuring logic components of the critical path to meet the predefined timing requirements.
8. The method of claim 7 , wherein the voltage value of the supply voltage is based on a worst-case voltage drop for the at least one voltage drop region.
9. A computer system, comprising:
a processor;
a memory; and
instructions residing in the memory executable in the processor for partitioning at least a portion of the integrated circuit into at least one voltage drop region, wherein the at least one voltage drop region inputs a supply voltage determined by a region-based voltage drop budget;
characterizing a time delay for a logic path segment in the at least one voltage drop region using the supply voltage inputted by the at least one voltage drop region; and
determining a critical path for the at least one voltage drop region using the time delay of the logic path segment.
10. The computer system of claim 9 , further comprising instructions for redesigning the critical path to meet the predefined timing requirements.
11. The computer system of claim 9 , wherein characterizing the time delay of the logic path segment comprises:
determining a set of logic components included in the logic path segment;
computing a time delay for each type of logic component using the supply voltage inputted by the voltage drop region; and
summing the time delays of the set of logic components.
12. The computer system of claim 9 , wherein the critical path is a min-time path.
13. The computer system of claim 9 , wherein the critical path is a max-time path.
14. The computer system of claim 9 , wherein the instructions for partitioning the at least a portion of the integrated circuit comprise instructions for:
ascertaining a voltage drop criteria for the integrated circuit;
analyzing the integrated circuit for worst-case voltage drop data using the voltage drop criteria;
partitioning the integrated circuit into another at least one voltage drop region based on the worst-case voltage drop data, wherein the another at least one voltage drop region is assigned a region-based voltage drop budget based on a worst-case voltage drop seen by the another at least one voltage drop region.
15. A method for verifying that an integrated circuit meets predefined timing requirements, comprising:
partitioning at least a portion of the integrated circuit into a set of voltage drop regions based on voltage drop data;
computing time delays for logic path segments in at least one of the set of voltage drop regions, wherein at least one of the set of voltage drop regions inputs a supply voltage determined by a region-based voltage drop budget;
identifying a critically timed path for the computed time delays; and
redesigning the critically timed path to meet a predefined timing requirement.