IP Library Granted Patent US 6,884,093
Granted Patent B2
US 6,884,093 · App. 10/246,508 · Granted Apr 26, 2005

Organic triodes with novel grid structures and method of production

Assignee: The Trustees of Princeton University
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Quick Facts
Patent No.
US 6,884,093
App. No.
10/246,508
Granted
Apr 26, 2005
Kind
B2
Abstract

An organic semiconductor device is provided. The device has a first electrode and a second electrode, with an organic semiconductor layer disposed between the first and second electrodes. An electrically conductive grid is disposed within the organic semiconductor layer, which has openings in which the organic semiconductor layer is present. At least one insulating layer is disposed adjacent to the electrically conductive grid, preferably such that the electrically conductive grid is completely separated from the organic semiconductor layer by the insulating layer. Methods of fabricating the device, and the electrically conductive grid in particular, are also provided. In one method, openings are formed in an electrically conductive layer with a patterned die, which is then removed. In another method, an electrically conductive layer and a first insulating layer are etched through the mask to expose portions of a first electrode. In yet another method, a patterned die is pressed into a first organic semiconductor layer to create texture in the surface of the first organic semiconductor layer, and then removed. An electrically conductive material is then deposited onto the first organic semiconductor layer from an angle to form a grid having openings as a result of the textured surface and the angular deposition. In each of the methods, insulating layers are preferably deposited or otherwise formed during the process to completely separate the electrically conductive layer from previously and subsequently deposited organic semiconductor layers.

Claims (22)

1. A method of fabricating a device, comprising the steps of:

(a) depositing a first organic semiconductor layer onto a first electrode;

(b) pressing a patterned die into the first organic semiconductor layer to create texture in the surface of the first organic semiconductor layer;

(c) removing the patterned die;

(d) depositing a conductor onto the organic semiconductor layer from an angle to form a grid having openings as a result of the textured surface and the angular deposition;

(e) depositing a second organic semiconductor layer over the grid and the first organic semiconductor layer;

(f) depositing a second electrode onto the second organic semiconductor layer.

2. The method of claim 1 , wherein the grid has a plurality of parallel electrically conductive lines.

3. The method of claim 1 , wherein the grid comprises an electrically conductive sheet having an array of openings therein.

4. The method of claim 1 , further comprising the steps of:

depositing a first insulating layer after step (c) and before step (d);

depositing a second insulating layer after step (d) and before step (e).

5. The method of claim 4 , wherein angle of deposition is varied during the deposition of either or both of the first and second insulating layers such that the conductor is completely separated from the semiconductor layer by the first and second insulating layers.

6. The method of claim 4 , further comprising the step of:

oxidizing any exposed surface of the conductor after depositing the second insulating layer and before step (e).

7. The method of claim 1 , wherein the first and second organic semiconducting layers comprise hole conducting materials, and the conductor comprises a metal having a work function greater than about 5 eV.

8. The method of claim 1 , wherein the first and second organic semiconducting layers comprise electron conducting materials, and the conductor comprises a metal having a work function less than about 4 eV.

9. The method of claim 4 , wherein the conductor comprises a material selected from the group consisting of gold and aluminum, and the first and second insulating layers comprise SiN x .

10. The method of claim 4 , wherein the first and second insulating layers comprise a material selected from the group consisting of SiN x and SiO 2 .

11. The method of claim 1 , wherein the conductor layer has a thickness of about 10-50 nm.

12. The method of claim 4 , wherein the first and second insulating layers each have a thickness of about 5-50 nm.

13. The method of claim 1 , wherein the first and second organic semiconductor layers each have a thickness of about 20-200 nm.

Assignments (1)
CONFIRMATORY LICENSE Recorded Mar 30, 2017
From: PRINCETON UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 042114/0210 →
Continuity (2)
Division 0967776500 · Oct 3, 2000
Related Publication 20030015698A1 · Jan 23, 2003