Semiconductor substrate with trenches for reducing substrate resistance
View Patent ↗In one embodiment of the present invention, a method for fabricating semiconductor devices comprises forming an active region about a front-side of a substrate. A plurality of trenches are then formed about a back-side of the substrate. A grid of banks separates the trenches. A conductive material is then applied to the back-side of the substrate. The trenches and the conductive material act to reduce the on-state resistance of the substrate and enhance thermal conductivity, while the grid of banks maintains the structural strength of the wafer.
1. A method of fabricating a semiconductor device, comprising:
forming an active region about a front-side of a substrate; and
forming a plurality of trenches about a back-side of the substrate, wherein the plurality of trenches form a grid of banks for maintaining structural strength of the substrate.
2. The method of fabricating a semiconductor device according to claim 1 , wherein the active region comprises a plurality of die regions, and wherein the plurality of trenches are spaced randomly apart with respect to the die regions.
3. The method of fabricating a semiconductor device according to claim 1 , wherein the active region comprises a plurality of die regions, and wherein two or more trenches are located within a region corresponding each die region.
4. The method of fabricating a semiconductor device according to claim 1 , wherein the trenches have sloped sides.
5. The method of fabricating a semiconductor device according to claim 1 , wherein the trenches reduce substrate on-state resistance.
6. The method of fabricating a semiconductor device according to claim 1 , further comprising:
depositing a metal layer on the back-side of the substrate, wherein the metal layer is deposited after forming the trenches.
7. The method of fabricating a semiconductor device according to claim 6 , wherein the trenches and the metal layer reduce substrate electrical resistance.
8. The method of fabricating a semiconductor device according to claim 6 , wherein the trenches and the metal layer increase substrate thermal conductivity.
9. The method of fabricating a semiconductor device according to claim 6 , wherein the trenches and the metal layer are adapted to increase reliability of the semiconductor device.
10. The method of fabricating a semiconductor device according to claim 1 , further comprising thinning the substrate before forming the plurality of trenches.
11. The method of fabricating a semiconductor device according to claim 1 , wherein a depth of the trenches exceed half a thickness of the substrate and does not extend to the active region.
12. A device die comprising:
a substrate;
an active region, wherein the active region is formed about a front-side of the substrate;
one or more trenches, wherein the trenches are formed about a back-side of the substrate; and
one or more banks forming a grid adapted to assure mechanical stiffness of the substrate, wherein the banks are formed about the back-side of the substrate between the trenches.
13. The device die according to claim 12 , wherein the trenches have sloped sides.
14. The device die according to claim 12 , wherein the trenches reduce substrate resistance.
15. The device die according to claim 12 , further comprising:
a conductive layer, wherein the conductive layer is formed on the back-side of the substrate after the trenches are formed.
16. The device die according to claim 15 , wherein the conductive layer is a tri-metal multi layer.
17. The device die according to claim 15 , wherein the conductive layer is a solder paste.
18. The device die according to claim 15 , wherein the conductive layer is a conductive epoxy.
19. The device die according to claim 15 , wherein the conductive layer is adapted to planarize the back-side of the substrate.
20. The device die according to claim 15 , wherein the trenches and the conductive layer reduce substrate electrical resistance.
21. The device die according to claim 15 , wherein the trenches and the conductive layer increase substrate thermal conductivity.
22. The device die according to claim 12 , wherein a depth of the trenches exceeds half a thickness of the substrate.
23. The device die according to claim 22 , wherein the depth of the trenches does not extend to the active region.
24. A wafer, comprising:
a substrate;
an active region, wherein the active region is formed about a front-side of the substrate, and wherein the active region further comprises a plurality of device dies separated by scribing borders;
a plurality of trenches, wherein the trenches are formed about a back-side of the substrate and wherein two or more trenches are placed in a region corresponding to each device die;
a grid of banks adapted to maintain structural strength of the wafer, wherein the banks are formed between the trenches; and
a conductive layer, wherein the conductive layer conformal coats the trenches and banks formed about the back-side of the substrate.
25. The wafer according to claim 24 , wherein the trenches have sloped sides.
26. The wafer according to claim 24 , wherein the plurality of trenches are spaced randomly apart with respect to the die regions.
27. The wafer according to claim 24 , wherein the width of the trenches are approximately one quarter the width of the die regions.
28. The wafer according to claim 24 , wherein the trenches are spaced to avoid the scribing borders.
29. The wafer according to claim 24 , wherein the trenches are not of sufficient length to form a straight groove in a pattern of the banks coinciding with the die regions.
30. The wafer according to claim 24 , wherein the trenches and the conductive layer are adapted to reduce substrate electrical resistance.
31. The wafer according to claim 24 , wherein the trenches and the conductive layer are adapted to increase substrate thermal conductivity.
32. The wafer according to claim 24 , wherein the length of the trenches are approximately one quarter the length of the die regions.
33. A method of fabricating a semiconductor device, comprising:
a means for forming an active region about a front-side of a substrate; and
a means for forming a plurality of trenches about a back-side of the substrate, whereby a grid of banks for maintaining structural strength of the substrate is formed between the trenches.
34. The method of fabricating a semiconductor device according to claim 33 , further comprising:
a means for depositing a conductive layer, wherein the conductive layer conformal coats the trenches and banks formed about the back-side of the substrate.
35. The method of fabricating a semiconductor device according to claim 34 , wherein the trenches and the conducting layer are adapted to reduce substrate electrical resistance.
36. The method of fabricating a semiconductor device according to claim 35 , wherein the trenches and the conducting layer are adapted to increase substrate thermal conductivity.
37. The method of fabricating a semiconductor device according to claim 36 , wherein the trenches and the conducting layer are adapted to increase reliability of the semiconductor device.
38. The method of fabricating a semiconductor device according to claim 37 , wherein the banks and conductive layer are adapted to assure mechanical stiffness of the substrate.