Patent Assignment
Reel/Frame 049440/0876
Security Interest
Recorded: 2019-06-12
Pages: 79
Assignors
VISHAY DALE ELECTRONICS, INC.
Executed: 2019-06-05
DALE ELECTRONICS, INC.
Executed: 2019-06-05
VISHAY DALE ELECTRONICS, LLC
Executed: 2019-06-05
VISHAY-DALE, INC.
Executed: 2019-06-05
VISHAY INTERTECHNOLOGY, INC.
Executed: 2019-06-05
SILICONIX INCORPORATED
Executed: 2019-06-05
VISHAY-SILICONIX, INC.
Executed: 2019-06-05
VISHAY-SILICONIX
Executed: 2019-06-05
VISHAY SPRAGUE, INC.
Executed: 2019-06-05
VISHAY EFI, INC.
Executed: 2019-06-05
SPRAGUE ELECTRIC COMPANY
Executed: 2019-06-05
VISHAY GENERAL SEMICONDUCTOR, INC.
Executed: 2019-06-05
Assignee
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
IL1-1145/54/63, P.O. BOX 6026, CHICAGO, ILLINOIS, 60603-6026
Covered Properties
(317)
Methods for Forming Lateral and Vertical Dmos Transistors
Patent:
4,682,405 →
Application:
06/757,582 →
Power Supply Having Dual Ramp Control Circuit
Patent:
4,674,020 →
Application:
06/808,575 →
Insulated Gate Transistor with Latching Inhibited
Patent:
4,779,123 →
Application:
06/808,904 →
Integrated Buried Zener Diode and Temperature Compensation Transistor
Patent:
4,766,469 →
Application:
06/816,593 →
Method for Manufacturing a Power Mos Transistor
Patent:
4,798,810 →
Application:
06/838,217 →
Fabrication of Double Diffused Metal Oxide Semiconductor Transistor
Patent:
4,716,126 →
Application:
06/871,006 →
Current Source with a Process Selectable Temperature Coefficient
Patent:
4,978,631 →
Application:
06/890,218 →
Manufacture of Trimmable High Value Polycrystalline Silicon Resistor
Patent:
4,707,909 →
Application:
06/894,418 →
Implantation of Ions into an Insulating Layer to Increase Planar Pn Junction Breakdown Voltage
Patent:
4,827,324 →
Application:
06/927,882 →
Method for Obtaining Regions of Dielectrically Isolated Single Crystal Silicon
Patent:
4,824,795 →
Application:
07/010,924 →
Method and Apparatus for Increasing Breakdown of a Planar Junction
Patent:
4,799,100 →
Application:
07/014,961 →
Switch Interface Circuit for Power Mosfet Gate Drive Control
Patent:
4,853,563 →
Application:
07/036,777 →
Ion Implantation of Thin Film CRSI2 and Sic Resistors
Patent:
4,759,836 →
Application:
07/084,541 →
Method of Bonding Semiconductor Wafers
Patent:
4,774,196 →
Application:
07/089,184 →
Dense Vertical J-Mos Transistor
Patent:
4,791,462 →
Application:
07/095,481 →
Dual-Gate High Density Fet
Patent:
4,835,586 →
Application:
07/099,452 →
Vertical Current Flow Field Effect Transistor
Patent:
5,164,325 →
Application:
07/107,725 →
Buried Gate Jfet
Patent:
4,845,051 →
Application:
07/115,076 →
High Voltage Level Shift Semiconductor Device
Patent:
4,890,146 →
Application:
07/133,710 →
A Power Mos Transistor with Equipotential Ring
Patent:
4,816,882 →
Application:
07/138,989 →
Grooved Dmos Process with Varying Gate Dielectric Thickness
Patent:
4,914,058 →
Application:
07/138,999 →
Method for Improved Alignment for Semiconductor Devices with Buried Layers
Patent:
4,936,930 →
Application:
07/141,877 →
Trench Power Mosfet Device
Patent:
4,967,245 →
Application:
07/167,617 →
High Voltage Drifted-Drain Mos Transistor
Patent:
4,794,436 →
Application:
07/195,436 →
Vertical Dmos Power Transistor with an Integral Operating Condition Sensor
Patent:
4,896,196 →
Application:
07/243,166 →
Power Transistor with Integrated Gate Resistor
Patent:
4,920,388 →
Application:
07/246,937 →
Complementary, Isolated Dmos Ic Technology
Patent:
5,156,989 →
Application:
07/268,839 →
Self-Aligned Ldd Lateral Dmos Transistor with High-Voltage Interconnect Capability
Patent:
5,055,896 →
Application:
07/285,842 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent:
5,072,266 →
Application:
07/290,546 →
Rugged Lateral Dmos Transistor Structure
Patent:
4,929,991 →
Application:
07/334,806 →
Method and Apparatus for Improving the on-Voltage Characteristics of a Semiconductor Device
Patent:
4,952,992 →
Application:
07/406,844 →
Mos Transistor with a Charge Induced Drain Extension
Patent:
5,108,940 →
Application:
07/451,518 →
Junction Field-Effect Transistor with a Novel Gate
Patent:
4,958,204 →
Application:
07/453,367 →
Optimization of Bv and Rds-on by Graded Doping in Ldd and Other High Voltage Ic
Patent:
5,132,753 →
Application:
07/498,170 →
Fuzed Solid Electrolyte Capacitor
Patent:
5,099,397 →
Application:
07/677,203 →
Molded Fuzed Solid Electrolyte Capacitor
Patent:
5,053,927 →
Application:
07/677,204 →
Method for Fabricating a High Voltage Mos Transistor
Patent:
5,132,235 →
Application:
07/678,578 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent:
5,298,442 →
Application:
07/762,103 →
High Voltage Mos Transistor with Reduced Parasitic Current Gain
Patent:
5,218,228 →
Application:
07/849,723 →
Vertical Current Flow Field Effect Transistor with Thick Insulator Over Non-Channel Areas
Patent:
5,298,781 →
Application:
07/910,864 →
Dmos Power Transistors with Reduced Number of Contacts Using Integrated Body-Source Connections
Patent:
5,410,170 →
Application:
08/047,723 →
Disconnect Switch Circuit to Power Head Retract in Hard Disk Drive Memories
Patent:
5,508,874 →
Application:
08/062,503 →
Method of Making Lightly-Doped Drain Dmos with Improved Breakdown Characteristics
Patent:
5,514,608 →
Application:
08/318,027 →
Punch-Through Field Effect Transistor
Patent:
5,592,005 →
Application:
08/415,009 →
Gas-Based Substrate Deposition Protection
Patent:
5,925,411 →
Application:
08/487,789 →
Method for Forming an Isolation Structure and a Bipolar Transistor on a Semiconductor Substrate
Patent:
5,648,281 →
Application:
08/647,073 →
Low-Side Bidirectional Battery Disconnect Switch
Patent:
6,590,440 →
Application:
08/800,972 →
Trench-Gated Schottky Diode with Integral Clamping Diode
Patent:
6,078,090 →
Application:
08/832,012 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent:
6,627,950 →
Application:
08/851,608 →
Multi-Tap Thin Film Inductor
Patent:
6,159,817 →
Application:
09/074,185 →
Vertical Trench-Gated Power Mosfet Having Stripe Geometry and High Cell Density
Patent:
6,204,533 →
Application:
09/089,250 →
Method of Forming Vertical Planar Dmosfet with Self-Aligned Contact
Patent:
6,277,695 →
Application:
09/293,380 →
Method of Forming Vertical Mosfet Device Having Voltage-Clamped Gate and Self-Aligned Contact
Patent:
6,268,242 →
Application:
09/314,621 →
Chip Scale Surface Mount Packages for Semiconductor Device and Process of Fabricating the Same
Patent:
6,316,287 →
Application:
09/395,094 →
Process of Fabricating a Chip Scale Surface Mount Package for Semiconductor Device
Patent:
6,271,060 →
Application:
09/395,095 →
Rf Modem Utilizing Saw Resonator and Correlator and Communications Transceiver Constructed Therefrom
Patent:
6,535,545 →
Application:
09/419,824 →
High Density Trench-Gated Power Mosfet
Patent:
6,348,712 →
Application:
09/428,299 →
Surface Mount Resistor
Patent:
6,184,775 →
Application:
09/441,434 →
Semiconductor Die Package Including Cup-Shaped Leadframe
Patent:
6,744,124 →
Application:
09/468,249 →
Method for Making Formed Surface Mount Resistor
Patent:
6,510,605 →
Application:
09/471,617 →
Method for Making Overlay Surface Mount Resistor
Patent:
6,401,329 →
Application:
09/471,622 →
Barrier Accumulation Mode Mosfet
Patent:
6,285,060 →
Application:
09/476,320 →
Method of Operation of Punch-Through Field Effect Transistor
Method and Apparatus for Delivering Power Simultaneously to Rechargeable Battery and Electronic Device
Patent:
6,300,744 →
Application:
09/502,546 →
Vertical Structure and Process for Semiconductor Wafer-Level Chip Scale Packages
Patent:
6,392,290 →
Application:
09/545,287 →
Rf Modem and Communications Transceiver Utilizing Saw Device and Pulse Shaping
Patent:
6,970,496 →
Application:
09/688,300 →
Overlay Surface Mount Resistor
Patent:
6,441,718 →
Application:
09/715,252 →
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Power Chip Resistor
Method of Fabricating Trench-Gated Power Mosfet
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Process for Manufacturing Trench Gated Mosfet Having Drain/Drift Region
Novel Current Limiting Technique for Hybrid Power Mosfet Circuits
Patent:
6,552,889 →
Application:
09/908,178 →
Trench Mis Device with Active Trench Corners and Thick Bottom Oxide and Method of Making the Same
Trench Mis Device with Reduced Gate-to-Drain Capacitance
Leadframe Having Slots in a Die Pad
Surge Current Chip Resistor
Method for Making Overlay Surface Mount Resistor
Apparatus for Tantalum Pentoxide Moisture Barrier in Film Resistors
Method of Making Trench-Gated Mosfet Having Cesium Gate Oxide Layer
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Trench Mis Device with Graduated Gate Oxide Layer
Method of Fabricating Trench Mis Device with Graduated Gate Oxide Layer
Encapsulation Method and Leadframe for Leadless Semiconductor Packages
Method of Fabricating Trench Junction Barrier Rectifier
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Thicker Oxide Formation at the Trench Bottom by Selective Oxide Deposition
Self-Aligned Differential Oxidation in Trenches by Ion Implantation
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Precision High-Frequency Capacitor on Semiconductor Substrate
Trench Mosfet Having Implanted Drain-Drift Region
Flip Chip Resistor and Its Manufacturing Method
Inductor Coil and Method for Making Same
Semiconductor Substrate with Trenches for Reducing Substrate Resistance
Patent:
6,858,471 →
Application:
10/247,906 →
Method of Forming Self Aligned Contacts for a Power Mosfet
Method for Making Trench Mis Device with Reduced Gate-to-Drain Capacitance
Semiconductor Assembly with Package Using Cup-Shaped Lead Frame
Method of Manufacturing a Resistor
Method for Making Trench Mosfet Having Implanted Drain-Drift Region
Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide and Process for Manufacturing the Same
Method of Forming Self Aligned Contacts for a Power Mosfet
Patent:
8,367,500 →
Application:
10/378,766 →
Method of Manufacturing Flip Chip Resistor
High Power Resistor Having an Improved Operating Temperature Range
Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Patent:
7,151,036 →
Application:
10/456,018 →
Triple-Diffused Trench Mosfet and Method of Fabricating the Same
Trench Mis Device with Thick Oxide Layer in Bottom of Gate Contact Trench
Closed Cell Trench Metal-Oxide-Semiconductor Field Effect Transistor
Method for Making High Power Resistor Having Improved Operating Temperature Range
Patent:
6,925,704 →
Application:
10/744,846 →
High Precision Power Resistors
Encapsulation Method for Leadless Semiconductor Packages
Surface Mount Flipchip Capacitor
Patent:
6,914,770 →
Application:
10/792,135 →
Surface Mount Chip Capacitor
Method for Making Overlay Surface Mount Resistor
Termination for Trench Mis Device Having Implanted Drain-Drift Region
Termination for Trench Mis Device Having Implanted Drain-Drift Region
Patent:
6,927,451 →
Application:
10/811,443 →
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent:
7,005,347 →
Application:
10/832,776 →
Super Trench Mosfet Including Buried Source Electrode and Method of Fabricating the Same
Drain Side Gate Trench Metal-Oxide-Semiconductor Field Effect Transistor
Patent:
6,906,380 →
Application:
10/846,339 →
Self Aligned Contact in a Semiconductor Device and Method of Fabricating the Same
Process for Manufacturing Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent:
7,335,946 →
Application:
10/898,431 →
Method of Forming Self Aligned Contacts for a Power Mosfet
Patent:
7,642,164 →
Application:
10/951,831 →
Method of Manufacturing a Resistor
Semiconductor Package Including Die Interposed Between Cup-Shaped Lead Frame and Lead Frame Having Mesas and Valleys
Method of Fabricating Semiconductor Package Including Die Interposed Between Cup-Shaped Lead Frame Having Mesas and Valleys
Method of Manufacturing a Drain Side Gate Trench Metal-Oxide-Semiconductor Field Effect Transistor
Patent:
7,344,945 →
Application:
11/023,327 →
Inductor Coil and Method for Making Same
Method of Manufacturing a Closed Cell Trench Mosfet
Surface Mount Electrical Resistor with Thermally Conductive, Electrically Insulative Filler and Method for Using Same
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Patent:
7,211,877 →
Application:
11/082,080 →
Trench-Gated Mis Device Having Thick Polysilicon Insulation Layer at Trench Bottom and Method of Fabricating the Same
Patent:
7,494,876 →
Application:
11/112,403 →
High Power Resistor Having an Improved Operating Temperature Range
Surface Mount Capacitor and Method of Making Same
Process of Fabricating Termination Region for Trench Mis Device
Triple-Diffused Trench Mosfet
Semiconductor Die Package Including Cup-Shaped Leadframe
Patent:
7,595,547 →
Application:
11/151,749 →
Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide
Electrostatic Discharge Protection Circuit for Integrated Circuits
Patent:
7,583,485 →
Application:
11/190,682 →
Termination for Trench Mis Device Having Implanted Drain-Drift Region
Method of Maufacturing Surface Mount Capacitor
Surface Mount Chip Capacitor
Trench Polysilicon Diode
Method of Fabricating Trench Mis Device with Thick Oxide Layer in Bottom of Trench
Adaptive Frequency Compensation for Dc-to-Dc Converter
Narrow Semiconductor Trench Structure
Ultra-Low Drain-Source Resistance Power Mosfet
Inductor Coil
Complete Power Management System Implemented in a Single Surface Mount Package
Complete Power Management System Implemented in a Single Surface Mount Package
Inductor with Thermally Stable Resistance
Chip-Scale Schottky Device
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Method for Making a High Current Low Profile Inductor
High Mobility Power Metal-Oxide Semiconductor Field-Effect Transistors
High-Density Power Mosfet with Planarized Metalization
Floating Gate Structure with High Electrostatic Discharge Performance
Super Trench Mosfet Including Buried Source Electrode
Process for Forming a Short Channel Trench Mosfet and Device Formed Thereby
Method for Making a High Current Low Profile Inductor
Power Mosfet Contact Metallization
Current Mode Boost Converter Using Slope Compensation
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent:
7,868,381 →
Application:
11/982,906 →
Trench Polysilicon Diode
Method for Making a High Current Low Profile Inductor
Self-Aligned Trench Mosfet and Method of Manufacture
Resistor, and Method for Making Same
Sulfuration Resistant Chip Resistor and Method for Making Same
Self-Repairing Field Effect Transistor
Narrow Semiconductor Trench Structure
Surface Mounted Chip Resistor with Flexible Leads
Stacked Trench Metal-Oxide-Semiconductor Field Effect Transistor Device
Electrophoretically Deposited Cathode Capacitor
Ultra-low drain-source resistance power MOSFET
Trench Metal Oxide Semiconductor with Recessed Trench Material and Remote Contacts
A Method of Making a Frame Package Array Device
Method of Manufacturing a Closed Cell Trench Mosfet
Patent:
7,833,863 →
Application:
12/107,738 →
High Current Density Power Field Effect Transistor
High Mobility Power Metal-Oxide Semiconductor Field-Effect Transistors
High Voltage Capacitors
Mosfet Active Area and Edge Termination Area Charge Balance
Resistor and Method for Making Same
Lightning Protection Device: Wet/Dry Field Sensitive Air Terminal
Encapsulation Techniques for Leadless Semiconductor Packages
Semiconductor Including Cup-Shaped Leadframe Packaging Techniques
Method for Making a High Current Low Profile Inductor
Metal Strip Resistor for Mitigating Effects of Thermal Emf
Super Junction Trench Power Mosfet Devices
Super Junction Trench Power Mosfet Device Fabrication
Electrostatic Discharge Protection Circuit for Integrated Circuits
Patent:
8,582,258 →
Application:
12/552,205 →
Split Gate Semiconductor Device with Curved Gate Oxide Profile
Semiconductor Device with Trench-Like Feed-Throughs
Trench Polysilicon Diode
Patent:
8,072,013 →
Application:
12/611,865 →
Semiconductor Packages Including Die and L-Shaped Lead and Method of Manufacture
Hermetically Sealed Wet Electrolytic Capacitor
Application:
12/759,769 →
Publication:
US 2010/0268292
Complete Power Management System Implemented in a Single Surface Mount Package
Super-High Density Trench Mosfet
Field Boosted Metal-Oxide-Semiconductor Field Effect Transistor
Power Switch with Active Snubber
Structures of and Methods of Fabricating Split Gate Mis Devices
System and Method for Substrate Wafer Back Side and Edge Cross Section Seals
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Transistor Structure with Feed-Through Source-to-Substrate Contact
Trench-Gated Mis Devices
Power Resistor
Structures and Methods of Fabricating Dual Gate Devices
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Method for Making a High Current Low Profile Inductor
Application:
13/109,576 →
Publication:
US 2012/0086535
Four-Terminal Resistor with Four Resistors and Adjustable Temperature Coefficient of Resistance
Inductor with Thermally Stable Resistance
High Powered Inductors Using a Magnetic Bias
Application:
13/213,877 →
Publication:
US 2011/0298572
Flux Transfer Device
Dual Lead Frame Semiconductor Package and Method of Manufacture
Trench Polysilicon Diode
Edge Termination for Super Junction Mosfet Devices
Mosfet Termination Trench
Hybrid Split Gate Semiconductor
Application:
13/460,567 →
Publication:
US 2012/0211828
Method of Forming a Hybrid Split Gate Simiconductor
Application:
13/460,600 →
Publication:
US 2012/0220092
Heat Spreader for Electrical Components
Semiconductor Device Having Reduced Gate Charges and Superior Figure of Merit
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Current Mode Boost Converter Using Slope Compensation
Circuit for Preventing Reverse Conduction
Resistor and Method for Making Same
Air Driven Reductant Delivery System
Highly Coupled Inductor
Application:
13/600,770 →
Publication:
US 2013/0055556
Breakdown Voltage Blocking Device
Power Mosfet Contact Metallization
Method for Making Inductor Coil Structure
Application:
13/720,618 →
Publication:
US 2013/0106562
Power Resistor with Integrated Heat Spreader
Trench Metal Oxide Semiconductor with Recessed Trench Material and Remote Contacts
Resistor and Method for Making Same
Adaptive Charge Balanced Mosfet Techniques
Integrated Circuit Element and Electronic Circuit for Light Emitting Diode Applications
Application:
13/750,404 →
Publication:
US 2013/0193851
Low Profile High Current Composite Transformer
Inductor with Thermally Stable Resistance
Stack Die Package
Method for Fabricating Stack Die Package
Current Limiting Systems and Methods
Gallium Nitride Power Semiconductor Device Having a Vertical Structure
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Zener Diode Haviing a Polysilicon Layer for Improved Reverse Surge Capability and Decreased Leakage Current
Semiconductor Structure with High Energy Dopant Implantation
Application:
14/058,933 →
Publication:
US 2015/0108568
Dual Trench Structure
Transistor Structure with Feed-Through Source-to-Substrate Contact
Trench Mos Device Having a Termination Structure with Multiple Field-Relaxation Trenches for High Voltage Applications
Electrical Press-Fit Pin for a Semiconductor Module
Resistor and Method of Manufacture
Patent:
9,396,849 →
Application:
14/203,234 →
Self-Aligned Trench Mosfet and Method of Manufacture
Resistor and Method for Making Same
Magnetic Components and Methods for Making Same
Resistor and Method for Making Same
Edge-Wound Resistor, Resistor Assembly, and Method of Making Same
Processes Used in Fabricating a Metal-Insulator-Semiconductor Field Effect Transistor
Dual Lead Frame Semiconductor Package and Method of Manufacture
Transistor Structure with Improved Unclamped Inductive Switching Immunity
Power Resistor with Integrated Heat Spreader
Dual Lead Frame Semiconductor Package and Method of Manufacture
Methods for Preventing Reverse Conduction
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Process for Forming a Short Channel Trench Mosfet and Device Formed Thereby
Thermally Sprayed Thin Film Resistor and Method of Making
Process for Forming a Planar Diode Using One Mask
GaN-BASED SCHOTTKY DIODE HAVING LARGE BOND PADS AND REDUCED CONTACT RESISTANCE
Patent:
9,281,417 →
Application:
14/627,013 →
Inductor with Thermally Stable Resistance
Modulated Super Junction Power Mosfet Devices
Semiconductor Device with Composite Trench and Implant Columns
Application:
14/659,415 →
Publication:
US 2015/0372132
Mosfet Termination Trench
Transistor Structure with Feed-Through Source-to-Substrate Contact
Semiconductor Device with Non-Uniform Trench Oxide Layer
Complete Power Management System Implemented in a Single Surface Mount Package
Application:
14/811,579 →
Publication:
US 2015/0331438
Zener Diode Haviing a Polysilicon Layer for Improved Reverse Surge Capability and Decreased Leakage Current
Edge Termination for Super-Junction Mosfets
Vertical Sense Devices in Vertical Trench Mosfet
Surface Mount Resistors and Methods of Manufacturing Same
System and Method for Substrate Wafer Back Side and Edge Cross Section Seals
Resistor and Method for Making Same
Semiconductor Device with Trench-Like Feed-Throughs
Transistor Structure with Improved Unclamped Inductive Switching Immunity
Semiconductor Device Having Multiple Gate Pads
Shielded Inductor and Method of Manufacturing
Nested Flat Wound Coils Forming Windings for Transformers and Inductors
Resistor and Method for Making Same
Resistor and Method of Manufacture
Patent:
9,934,891 →
Application:
15/213,199 →
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Molded Body and Electrical Device Having a Molded Body for High Voltage Applications
Split Gate Semiconductor Device with Curved Gate Oxide Profile
Trench Mosfet with Self-Aligned Body Contact with Spacer
Mosfet Active Area and Edge Termination Area Charge Balance
Method for Fabricating Stack Die Package
Dual Lead Frame Semiconductor Package and Method of Manufacture
Edge Termination for Super-Junction Mosfets
Semiconductor Device with Non-Uniform Trench Oxide Layer
Vertical Sense Devices in Vertical Trench Mosfet
High-Electron-Mobility Transistor Devices
High-Electron-Mobility Transistor with Buried Interconnect
Transistor Structure with Improved Unclamped Inductive Switching Immunity
Inductor Having High Current Coil with Low Direct Current Resistance
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Adaptive Charge Balanced Edge Termination
Molded Body and Electrical Device Having a Molded Body for High Voltage Applications
Modulated Super Junction Power Mosfet Devices
Power Semiconductor Device with Optimized Field-Plate Design
Devices and Methods for Driving a Semiconductor Switching Device
Protection Circuits with Negative Gate Swing Capability
High Electron Mobility Transistor Esd Protection Structures
Surface Mount Resistors and Methods of Manufacturing Same
Resistor with Upper Surface Heat Dissipation
Split Gate Semiconductor with Non-Uniform Trench Oxide
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
High-Electron-Mobility Transistor Devices
Semiconductor Chip Package
Patent:
466,873 →
Application:
29/151,024 →
Semiconductor Chip Package
Patent:
472,528 →
Application:
29/151,069 →
Edge-Wound Resistor
Patent:
758,970 →
Application:
29/491,946 →
Edge-Wound Resistor
Patent:
855,569 →
Application:
29/567,803 →
Semiconductor Device Having Reduced Gate Charges and Superior Figure of Merit
Application:
61/487,627 →
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.