IP Library Granted Patent US 8,697,571
Granted Patent B2
US 8,697,571 · App. 13/654,230 · Granted Apr 15, 2014

Power MOSFET contact metallization

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Quick Facts
Patent No.
US 8,697,571
App. No.
13/654,230
Granted
Apr 15, 2014
Kind
B2
Abstract

A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Claims (11)

1. A method of fabricating a structure, said method comprising:

depositing a barrier layer, wherein said barrier layer is deposited over and in contact with all surfaces of an insulator except for a second surface of said insulator that is in contact with a first surface of a substrate having a semiconductor device formed therein, wherein said barrier layer is also deposited over and in contact with said substrate in a contact area between said insulator and an adjacent insulator;

depositing a first metallized layer over said barrier layer; and

etching said first metallized layer to form an electrical contact in said contact area, wherein a substantially even surface is formed by combining a surface of said barrier layer and a surface of said electrical contact, wherein said barrier layer is between and in contact with said substrate and said electrical contact, and said semiconductor device is adjacent to and underneath said insulator and entirely isolated physically from said electrical contact and from said barrier layer by said insulator, said semiconductor device electrically coupled to said electrical contact.

2. The method of claim 1 wherein said first metallized layer comprises tungsten.

3. The method of claim 1 wherein said first metallized layer is deposited using chemical vapor deposition.

4. The method of claim 1 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

5. The method of claim 1 further comprising:

depositing a second metallized layer subsequent to said etching; and

etching said second metallized layer to form an electrical connector coupled to said electrical contact.

6. The method of claim 5 wherein said second metallized layer comprises aluminum.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED
Reel/Frame 049785/0771 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Sep 5, 2013
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 031170/0001 →