IP Library › Granted Patent US 7,238,551
Granted Patent B2
US 7,238,551 · App. 10/996,149 · Granted Jul 3, 2007

Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys

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Quick Facts
Patent No.
US 7,238,551
App. No.
10/996,149
Granted
Jul 3, 2007
Kind
B2
Abstract

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Claims (40)

1. A method of fabricating a semiconductor package comprising:

providing a lower lead frame, said lower lead frame having at least a first contact;

forming a plurality of raised mesas in said first contact, said mesas having top surfaces and being separated by valleys;

dispensing a first plurality of solder paste drops only on said top surfaces of said mesas;

placing a semiconductor die on said first plurality of solder paste drops;

performing a first reflow of said first plurality of solder paste drops so as form a first solder layer between said die and said first contact, said first reflow causing the first solder layer to flow into said valleys thereby decreasing a separation distance between said die and said first contact;

dispensing a second plurality of solder paste drops on a top surface of said die;

placing an upper lead frame on said second plurality of solder paste drops, said upper lead frame comprising bent portions at opposite ends of said upper lead frame, each of said bent portions terminating in a foot, said bent portions extending downward around opposite edges of said die;

performing a second reflow of said plurality of solder paste drops and said first solder layer.

2. The method of claim 1 wherein said lower lead frame further comprises at least two outside contacts, said outside contacts being located on opposite sides of said first contact, said method comprising dispensing a third plurality of solder paste drops on each of in said outside contacts and bringing said feet into contact with said third plurality of solder drops.

3. The method of claim 1 wherein during said second reflow at least a portion of said first solder layer flows from said valleys.

4. The method of claim 1 wherein a vertical distance between said first contact and said die increases during said second reflow.

5. The method of claim 1 wherein forming said mesa comprises etching said first contact so as to form said valleys.

6. The method of claim 2 comprising:

forming a cavity in a top surface of each of said outside contacts;

dispensing said third plurality of solder paste drops in said cavities.

7. A method of fabricating a package comprising a MOSFET die, the MOSFET die having a source terminal and a gate terminal on a first surface of the die and a drain terminal on a second surface of the die, the method comprising:

providing a lower lead frame, said lower lead frame comprising a source contact, a gate contact and at least two drain contacts,

providing an upper lead frame, said upper lead frame being cup-shaped and having at least two bent portions on opposite sides of said upper lead frame, said bent portions terminating in feet;

forming a plurality of mesas in said source contact, said mesas having top surfaces and being separated by valleys;

forming at least one cavity in each of said drain contacts;

dispensing a plurality of solder paste drops on said source contact, said paste drops resting on said top surfaces of said mesas but not filling said valleys;

dispensing solder paste on said gate contact;

placing said MOSFET die on said solder paste drops, the source terminal of said die being in contact with said plurality of solder paste drops, the gate terminal of said die being in contact with said solder paste on said gate contact;

performing a first reflow of said solder paste drops and said solder paste on said gate contact so as form a first solder layer between said source terminal and said source contact and a second solder layer between said gate terminal and said gate contact, said first reflow causing the first solder layer to flow into said valleys thereby decreasing a separation distance between said die and said source and gate contacts;

dispensing solder paste into said at least one cavity in each of said drain contacts;

dispensing solder paste on said drain terminal of said die;

placing said upper lead frame on said solder paste on said drain terminal and said solder paste in said at least one cavity, the feet of said upper lead frame resting on said solder paste in said at least one cavity; and

performing a second reflow of said first solder layer and said solder paste on said drain terminal and in said at least one cavity, said second reflow forming a second solder layer between said upper lead frame and said die, said second reflow causing said die to lift from said source and gate contacts and causing at least a portion of said first solder layer to flow out of said valleys.

8. The method of claim 7 comprising forming longitudinal openings in said upper lead frame at the locations of said at least two bent portions.

9. The method of claim 7 comprising forming four bent portions in said upper lead frame.

10. The method of claim 7 wherein said mesas are formed by etching said lower lead frame.

11. The method of claim 7 wherein said mesas are formed by stamping said lower lead frame.

12. The method of claim 7 comprising forming a groove in a lower surface of said upper lead frame.

13. The method of claim 12 wherein said groove is X-shaped.

14. The method of claim 12 comprising forming a series of parallel grooves the lower surface of said upper lead frame.

15. The method of claim 7 comprising applying molding compound to said leadframes and die after said second reflow, said molding compound flowing into said valleys of said source contact.

16. The method of claim 7 where a thickness ratio between said second solder layer and said first solder layer after said second reflow is in the range of 1:2 to 1:10.

17. The method of claim 7 wherein a thickness of said first solder layer is greater than 2.0 mils and a thickness of said second solder layer is less than 1.2 mils.

18. The method of claim 17 wherein a thickness of said first solder layer is 3.5 mils and a thickness of said second solder layer is 0.8 mils.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
RELEASE OF SECURITY INTEREST Recorded Dec 14, 2010
From: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
To: VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION; VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION; VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION; SILICONIX INCORPORATED, A DELAWARE CORPORATION; VISHAY MEASUREMENTS GROUP, INC., A DELAWARE CORPORATION; VISHAY GENERAL SEMICONDUCTOR, LLC, F/K/A GENERAL SEMICONDUCTOR, INC., A DELAWARE LIMITED LIABILITY COMPANY; VISHAY VITRAMON, INCORPORATED, A DELAWARE CORPORATION; YOSEMITE INVESTMENT, INC., AN INDIANA CORPORATION
Reel/Frame 025489/0184 →
SECURITY AGREEMENT Recorded Mar 2, 2010
From: VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC; VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY MEASUREMENTS GROUP, INC.
To: COMERICA BANK, AS AGENT
Reel/Frame 024006/0515 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2005
From: KASEM, MOHAMMED; OWYANG, KING; JAUNAY, SERGE ROBERT; KUO, FRANK; MAO, SEN; OU, OSCAR; WANG, PETER; CHEN, CHANG-SHENG
To: SILICONIX INCORPORATED
Reel/Frame 016120/0907 →