IP Library › Assignment 025675/0001
Patent Assignment
Reel/Frame 025675/0001

Security Agreement

Recorded: 2011-01-21 Pages: 107
Assignors
VISHAY INTERTECHNOLOGY, INC.
Executed: 2010-12-01
VISHAY DALE ELECTRONICS, INC.
Executed: 2010-12-01
SILICONIX INCORPORATED
Executed: 2010-12-01
VISHAY SPRAGUE, INC.
Executed: 2010-12-01
Assignee
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
1111 FANNIN ST., FLOOR 10, HOUSTON, TEXAS, 77002
Covered Properties (380)
Methods for Forming Lateral and Vertical Dmos Transistors
Patent: 4,682,405 →
Application: 06/757,582 →
Power Supply Having Dual Ramp Control Circuit
Patent: 4,674,020 →
Application: 06/808,575 →
Insulated Gate Transistor with Latching Inhibited
Patent: 4,779,123 →
Application: 06/808,904 →
Integrated Buried Zener Diode and Temperature Compensation Transistor
Patent: 4,766,469 →
Application: 06/816,593 →
Method for Manufacturing a Power Mos Transistor
Patent: 4,798,810 →
Application: 06/838,217 →
Fabrication of Double Diffused Metal Oxide Semiconductor Transistor
Patent: 4,716,126 →
Application: 06/871,006 →
Current Source with a Process Selectable Temperature Coefficient
Patent: 4,978,631 →
Application: 06/890,218 →
Manufacture of Trimmable High Value Polycrystalline Silicon Resistor
Patent: 4,707,909 →
Application: 06/894,418 →
Implantation of Ions into an Insulating Layer to Increase Planar Pn Junction Breakdown Voltage
Patent: 4,827,324 →
Application: 06/927,882 →
Method for Obtaining Regions of Dielectrically Isolated Single Crystal Silicon
Patent: 4,824,795 →
Application: 07/010,924 →
Method and Apparatus for Increasing Breakdown of a Planar Junction
Patent: 4,799,100 →
Application: 07/014,961 →
Switch Interface Circuit for Power Mosfet Gate Drive Control
Patent: 4,853,563 →
Application: 07/036,777 →
Ion Implantation of Thin Film CRSI2 and Sic Resistors
Patent: 4,759,836 →
Application: 07/084,541 →
Method of Bonding Semiconductor Wafers
Patent: 4,774,196 →
Application: 07/089,184 →
Dense Vertical J-Mos Transistor
Patent: 4,791,462 →
Application: 07/095,481 →
Dual-Gate High Density Fet
Patent: 4,835,586 →
Application: 07/099,452 →
Vertical Current Flow Field Effect Transistor
Patent: 5,164,325 →
Application: 07/107,725 →
Buried Gate Jfet
Patent: 4,845,051 →
Application: 07/115,076 →
High Voltage Level Shift Semiconductor Device
Patent: 4,890,146 →
Application: 07/133,710 →
A Power Mos Transistor with Equipotential Ring
Patent: 4,816,882 →
Application: 07/138,989 →
Grooved Dmos Process with Varying Gate Dielectric Thickness
Patent: 4,914,058 →
Application: 07/138,999 →
Method for Improved Alignment for Semiconductor Devices with Buried Layers
Patent: 4,936,930 →
Application: 07/141,877 →
Trench Power Mosfet Device
Patent: 4,967,245 →
Application: 07/167,617 →
High Voltage Drifted-Drain Mos Transistor
Patent: 4,794,436 →
Application: 07/195,436 →
Vertical Dmos Power Transistor with an Integral Operating Condition Sensor
Patent: 4,896,196 →
Application: 07/243,166 →
Power Transistor with Integrated Gate Resistor
Patent: 4,920,388 →
Application: 07/246,937 →
Complementary, Isolated Dmos Ic Technology
Patent: 5,156,989 →
Application: 07/268,839 →
Self-Aligned Ldd Lateral Dmos Transistor with High-Voltage Interconnect Capability
Patent: 5,055,896 →
Application: 07/285,842 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent: 5,072,266 →
Application: 07/290,546 →
Rugged Lateral Dmos Transistor Structure
Patent: 4,929,991 →
Application: 07/334,806 →
Method and Apparatus for Improving the on-Voltage Characteristics of a Semiconductor Device
Patent: 4,952,992 →
Application: 07/406,844 →
Mos Transistor with a Charge Induced Drain Extension
Patent: 5,108,940 →
Application: 07/451,518 →
Junction Field-Effect Transistor with a Novel Gate
Patent: 4,958,204 →
Application: 07/453,367 →
Optimization of Bv and Rds-on by Graded Doping in Ldd and Other High Voltage Ic
Patent: 5,132,753 →
Application: 07/498,170 →
Fuzed Solid Electrolyte Capacitor
Patent: 5,099,397 →
Application: 07/677,203 →
Molded Fuzed Solid Electrolyte Capacitor
Patent: 5,053,927 →
Application: 07/677,204 →
Method for Fabricating a High Voltage Mos Transistor
Patent: 5,132,235 →
Application: 07/678,578 →
Lightly-Doped Drain Mosfet with Improved Breakdown Characteristics
Patent: 5,386,136 →
Application: 07/697,356 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent: 5,298,442 →
Application: 07/762,103 →
Mos Transistor with a Charge Induced Drain Extension
Patent: 5,243,212 →
Application: 07/802,352 →
High Voltage Mos Transistor with Reduced Parasitic Current Gain
Patent: 5,218,228 →
Application: 07/849,723 →
Threshold Adjustment in Fabricating Vertical Dmos Devices
Patent: 5,248,627 →
Application: 07/854,162 →
Driver Circuit for Sinking Current to Two Supply Voltages
Patent: 5,296,765 →
Application: 07/855,377 →
Bulk Metal Chip Resistor
Patent: 5,287,083 →
Application: 07/860,403 →
Power Device with Buffered Gate Shield Region
Patent: 5,430,314 →
Application: 07/873,423 →
Low on-Resistance Power Mos Technology
Patent: 5,304,831 →
Application: 07/881,589 →
Monolythic Multilayer Chip Inductor and Method for Making Same
Patent: 5,302,932 →
Application: 07/881,856 →
Isolated Dmos Ic Technology
Patent: 5,485,027 →
Application: 07/904,402 →
Vertical Current Flow Field Effect Transistor with Thick Insulator Over Non-Channel Areas
Patent: 5,298,781 →
Application: 07/910,864 →
Field Effect Trench Transistor Having Lightly Doped Epitaxial Region on the Surface Portion Thereof
Patent: 5,910,669 →
Application: 07/918,954 →
High Voltage Transistor Having Edge Termination Utilizing Trench Technology
Patent: 5,430,324 →
Application: 07/918,996 →
Trenched Dmos Transistor Fabrication Using Six Masks
Patent: 5,316,959 →
Application: 07/928,909 →
Low Temperature Oxide Layer Over Field Implant Mask
Patent: 5,328,866 →
Application: 07/949,288 →
Method of Making Vertical Current Flow Field Effect Transistor
Patent: 5,576,245 →
Application: 07/978,201 →
Bicmos Structure
Patent: 5,422,508 →
Application: 08/026,930 →
Method for Forming a Bicdmos
Patent: 5,374,569 →
Application: 08/026,932 →
Short Channel Trenched Dmos Transistor
Patent: 5,341,011 →
Application: 08/031,798 →
Lightly-Doped Drain Mosfet with Improved Breakdown Characteristics
Patent: 5,374,843 →
Application: 08/040,684 →
Method for Reducing on Resistance and Improving Current Characteristics of a Mosfet
Patent: 5,306,656 →
Application: 08/046,058 →
Dmos Power Transistors with Reduced Number of Contacts Using Integrated Body-Source Connections
Patent: 5,410,170 →
Application: 08/047,723 →
Threshold Adjustment in Vertical Dmos Devices
Patent: 5,465,000 →
Application: 08/062,370 →
Disconnect Switch Circuit to Power Head Retract in Hard Disk Drive Memories
Patent: 5,508,874 →
Application: 08/062,503 →
Push-Pull Output Stage for Driving Motors Which Generates Auxiliary Voltage Supply
Patent: 5,377,094 →
Application: 08/062,504 →
Contact Geometry for Improved Lateral Mosfet
Patent: 5,412,239 →
Application: 08/062,507 →
Head-Retract Circuit for Moving Media Storage Apparatus
Patent: 5,455,496 →
Application: 08/062,968 →
Apparatus for Generating Positive and Negative Supply Rails from Operating Motor Control Circuit
Patent: 5,459,654 →
Application: 08/062,969 →
Floating Drive Technique for Reverse Battery Protection
Patent: 5,539,610 →
Application: 08/067,365 →
Junction-Isolated Floating Diode
Patent: 5,414,292 →
Application: 08/067,372 →
Reverse Battery Protection Device Containing Power Mosfet
Patent: 5,517,379 →
Application: 08/067,373 →
Metal Crossover in High Voltage Ic with Graduated Doping Control
Patent: 5,426,325 →
Application: 08/101,886 →
Low Threshold Voltage Epitaxial Dmos Technology
Patent: 5,479,037 →
Application: 08/131,114 →
Bidirectional Blocking Lateral Mosfet with Improved On-Resistance
Patent: 5,420,451 →
Application: 08/160,539 →
Gate Drive Technique for a Bidirectional Blocking Lateral Mosfet
Patent: 5,510,747 →
Application: 08/160,560 →
Low on-Resistance Power Mos Technology
Patent: 5,429,964 →
Application: 08/180,265 →
Method of Making Bicdmos Structures
Patent: 5,416,039 →
Application: 08/225,270 →
Bicdmos Structures
Patent: 5,426,328 →
Application: 08/226,419 →
Low Temperature Oxide Layer Over Field Implant Mask
Patent: 5,439,842 →
Application: 08/236,299 →
Method of Making Power Device with Buffered Gate Shield Region
Patent: 5,445,978 →
Application: 08/242,519 →
Trenched Dmos Transistor with Channel Block at Cell Trench Corners
Patent: 5,468,982 →
Application: 08/253,527 →
Reliability Test Method for Semiconductor Trench Devices
Patent: 5,486,772 →
Application: 08/268,755 →
Method for Fabricating a Short Channel Trenched Dmos Transistor
Patent: 5,474,943 →
Application: 08/289,358 →
Voltage Converter with Frequency Shift Protection Against Overload Current
Patent: 5,528,483 →
Application: 08/295,271 →
Method of Making Lightly-Doped Drain Dmos with Improved Breakdown Characteristics
Patent: 5,514,608 →
Application: 08/318,027 →
Bidirectinal Blocking Lateral Mosfet with Improved On-Resistance
Patent: 5,451,533 →
Application: 08/318,323 →
Bicdmos Process Technology
Patent: 5,559,044 →
Application: 08/323,950 →
Protective Circuit for Protecting Load Against Excessive Input Voltage
Patent: 5,585,991 →
Application: 08/325,860 →
Electrostatic Discharge Protection Device for Integrated Circuit
Patent: 5,545,909 →
Application: 08/326,172 →
Voltage Regulator Having Improved Stability
Patent: 5,559,424 →
Application: 08/326,408 →
Surface Mount Resistor and Method for Making Same
Patent: 5,604,477 →
Application: 08/350,960 →
Structure and Fabrication of Power Mosfets, Including Termination Structures
Patent: 5,521,409 →
Application: 08/362,674 →
Lateral Power Mosfet Having Metal Strap Layer to Reduce Distributed Resistance
Patent: 5,767,546 →
Application: 08/367,388 →
Vertical Power Mosfet Having Thick Metal Layer to Reduce Distributed Resistance
Patent: 5,665,996 →
Application: 08/367,486 →
Low-Side Bidirectional Battery Disconnect Switch
Patent: 5,689,209 →
Application: 08/367,515 →
Trench Field Effect Transistor with Reduced Punch-Through Susceptibility and Low Rdson
Patent: 5,558,313 →
Application: 08/386,895 →
Band Gap Voltage Compensation Circuit
Patent: 5,596,265 →
Application: 08/388,535 →
Output Control Circuit for a Voltage Regulator
Patent: 5,506,496 →
Application: 08/389,705 →
Punch-Through Field Effect Transistor
Patent: 5,592,005 →
Application: 08/415,009 →
Method for Making Termination Structure for Power Mosfet
Patent: 5,597,765 →
Application: 08/423,588 →
Method of Making a Trench Mosfet with Multi-Resistivity Drain to Provide Low on-Resistance by Varying Dopant Concentration in Epitaxial Layer
Patent: 5,674,766 →
Application: 08/429,414 →
Method for Fabricating High Voltage Transistor Having Trenched Termination
Patent: 5,605,852 →
Application: 08/444,336 →
Method of Making a Field Effect Trench Transistor Having Lightly Doped Epitaxial Region on the Surface Portion Thereof
Patent: 5,532,179 →
Application: 08/447,484 →
Voltage-Clamped Power Accumulation-Mode Mosfet
Patent: 5,856,692 →
Application: 08/459,054 →
Bidirectional Blocking Accumulation-Mode Trench Power Mosfet
Patent: 5,661,322 →
Application: 08/459,559 →
Method for Forming a Lateral Mos Transistor Having Lightly Doped Drain Formed Along with Other Transistors in the Same Substrate
Patent: 5,541,125 →
Application: 08/463,165 →
Mos Transistor Having Adjusted Threshold Voltage Formed Along with Other Transistors
Patent: 5,618,743 →
Application: 08/463,417 →
Method for Forming a Bipolar Transistor Having Selected Breakdown Voltage
Patent: 5,541,123 →
Application: 08/463,647 →
Pmos Transistors with Different Breakdown Voltages Formed in the Same Substrate
Patent: 5,583,061 →
Application: 08/464,435 →
Method for Forming a Zener Diode Region and an Isolation Region
Patent: 5,547,880 →
Application: 08/464,978 →
Methodfor Forming a Elecrostatic Discharge Protection Device for Ineg- Rated Circuit
Patent: 5,677,205 →
Application: 08/472,943 →
Method of Forming a Lateral Field Effect Transistor Having Reduced Drain-to-Source On-Resistance
Patent: 5,750,416 →
Application: 08/479,308 →
Pwm Multiplexed Solenoid Driver
Patent: 5,621,604 →
Application: 08/480,469 →
Threshold Adjustment in Field Effect Semiconductor Devices
Patent: 5,726,477 →
Application: 08/482,341 →
Method of Making a Trench Mosfet with Heavily Doped Delta Layer to Provide Low On-Resistance
Patent: 5,688,725 →
Application: 08/482,357 →
Electrostatic Discharge Protection Device for Integrated Circuit
Patent: 5,654,574 →
Application: 08/486,280 →
Gas-Based Substrate Deposition Protection
Patent: 5,925,411 →
Application: 08/487,789 →
High Density Trenched Dmos Transistor
Patent: 5,689,128 →
Application: 08/533,814 →
Trenched Dmos Transistor with Buried Layer for Reduced on-Resistance and Ruggedness
Patent: 5,629,543 →
Application: 08/537,157 →
Switching Device Including Poer Mosfet with Internal Power Supply Circuit
Patent: 5,726,594 →
Application: 08/538,105 →
Bidirectional Current Blocking Mosfet for Battery Disconnect Switching Including Protection Against Reverse Connected Battery Charger
Patent: 5,682,050 →
Application: 08/541,345 →
Multiple Gated Mosfet for Use in Dc-Dc Converter
Patent: 5,616,945 →
Application: 08/542,611 →
Separate Circuit Devices in an Intra-Package Configuration and Assembly Techniques
Patent: 6,066,890 →
Application: 08/556,369 →
Bidirectional Blocking Lateral Mosfet with Improved On-Resistance
Patent: 5,612,566 →
Application: 08/569,334 →
Low Voltage Mosfet with Low on-Resistance and High Breakdown Voltage
Patent: 5,939,752 →
Application: 08/570,876 →
Closed-Loop Frequency-to-Current Converter with Integrable Capacitances
Patent: 5,736,879 →
Application: 08/594,676 →
Commutation Delay Generator for a Multiphase Brushless Dc Motor
Patent: 5,767,643 →
Application: 08/595,812 →
Trenched Dmos Transistor Fabrication Using Seven Masks and Having Thick Termination Region Oxide
Patent: 5,639,676 →
Application: 08/603,047 →
Surface Mount and Flip Chip Technology for Total Integrated Circuit Isolation
Patent: 5,757,081 →
Application: 08/603,512 →
Trenched Dmos Transistor with Lightly Doped Tub
Patent: 5,821,583 →
Application: 08/610,563 →
Vertical Power Mosfet Having Reduced Sensitivity to Variations in Thickness of Epitaxial Layer
Patent: 5,814,858 →
Application: 08/616,393 →
Trenched Dmos Transistor Having Thick Field Oxide in Termination Region
Patent: 5,578,851 →
Application: 08/625,639 →
Edge Termination Structure for Power Mosfet
Patent: 5,614,751 →
Application: 08/632,052 →
Surface Mount and Flip Chip Technology with Diamond Film Passivation for Total Integrated Circuit Isolation
Patent: 5,767,578 →
Application: 08/634,957 →
Gate Drive Technique for a Bidirectional Blocking Lateral Mosfet
Patent: 5,731,732 →
Application: 08/636,258 →
Method of Blocking Biderectional Flow of Current
Patent: 5,747,891 →
Application: 08/636,367 →
Fabrication of High-Density Trench Dmos Using Sidewall Spacers
Patent: 5,904,525 →
Application: 08/646,593 →
Method for Forming an Isolation Structure and a Bipolar Transistor on a Semiconductor Substrate
Patent: 5,648,281 →
Application: 08/647,073 →
Three-Terminal Power Mosfet Switch for Use as Synchronous Rectifier or Voltage Clamp
Patent: 5,744,994 →
Application: 08/648,266 →
Pseudo-Schottky Diode
Patent: 5,818,084 →
Application: 08/648,334 →
Four-Terminal Power Mosfet Switch Having Reduced Threshold Voltage and On-Resistance
Patent: 5,689,144 →
Application: 08/649,747 →
Long Channel Trench-Gated Power Mosfet Having Fully Depleted Body Region
Patent: 5,998,834 →
Application: 08/651,232 →
Trench Field Effect Transistor with Reduced Punch-Through Susceptibility and Low Rdson
Patent: 5,981,344 →
Application: 08/658,115 →
Monolithic Thick Film Inductor
Patent: 5,986,533 →
Application: 08/665,788 →
Method for Fabricating an Mos Capacitor Using Zener Diode Region
Patent: 5,643,820 →
Application: 08/667,219 →
Trench Mosfet with Multi-Resistivity Drain to Provide Low On-Resistance
Patent: 5,895,952 →
Application: 08/701,035 →
Synchronous Current Sharing Pulse Width Modulator
Patent: 5,808,453 →
Application: 08/701,114 →
Zener Diodes on the Same Wafer with Bicdmos Structures
Patent: 5,751,054 →
Application: 08/705,910 →
Trenched Field Effect Transistor with Pn Depletion Barrier
Patent: 5,917,216 →
Application: 08/742,326 →
Method of Fabricating a Field Effect Transistor
Patent: 6,090,716 →
Application: 08/767,708 →
Dmos Power Transistor with Reduced Number of Contacts Using Integrated Body-Source Connections
Patent: 5,866,931 →
Application: 08/777,636 →
Vertical Power Mosfet Having Thick Metal Layer to Reduce Distributed Resistance
Patent: 6,066,877 →
Application: 08/779,176 →
Low-Side Bidirectional Battery Disconnect Switch
Patent: 6,590,440 →
Application: 08/800,972 →
Multiple Gated Mosfet for Use in Dc-Dc Converter
Patent: 5,973,367 →
Application: 08/828,474 →
Trench-Gated Schottky Diode with Integral Clamping Diode
Patent: 6,078,090 →
Application: 08/832,012 →
Trench-Gated Power Mosfet with Protective Diode
Patent: 5,998,836 →
Application: 08/846,688 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent: 6,627,950 →
Application: 08/851,608 →
Method of Forming Electrostatic Discharge Protection Device for Integrated Circuit
Patent: 5,877,534 →
Application: 08/873,781 →
Method of Makng Monolithic Thick Film Inductor
Patent: 5,970,604 →
Application: 08/881,480 →
Bidirectional Trench Gated Power Mosfet with Submerged Body Bus Extending Underneath Gate Trench
Patent: 5,877,538 →
Application: 08/884,826 →
Trench Mosfet with Heavily Doped Delta Layer to Provide Low on Resistance
Patent: 6,008,520 →
Application: 08/895,497 →
Safety Switch for Lithium Ion Battery
Patent: 5,909,103 →
Application: 08/899,001 →
Method and Apparatus for Providing Gate Drive Voltage to Switching Device
Patent: 5,909,139 →
Application: 08/907,216 →
Integrated Circuit Die Having Thick Bus to Reduce Distributed Resistance
Patent: 5,945,709 →
Application: 08/907,276 →
Low Resistance Power Mosfet or Other Device Containing Silicon-Germanium Layer
Patent: 6,239,463 →
Application: 08/919,386 →
Trench- Gated Power Mosfet with Protective Diode Having Adjustable Breakdown Voltage
Patent: 5,998,837 →
Application: 08/919,523 →
Trench-Gated Mosfet with Bidirectional Voltage Clamping
Patent: 6,049,108 →
Application: 08/920,330 →
Planar Dmos Transistor Fabricated by a Three Mask Process
Patent: 5,923,979 →
Application: 08/922,672 →
Thick Film Low Value High Frequency Inductor, and Method of Making the Same
Patent: 5,922,514 →
Application: 08/936,193 →
Three-Terminal Power Mosfet Switch for Use as Synchronous Rectifier or Voltage Clamp
Patent: 5,929,690 →
Application: 08/937,941 →
Trench-Gated Mosfet with Integral Temperature Detection Diode
Patent: 6,046,470 →
Application: 08/946,613 →
Short Circuit Protected Dc-Dc Converter Using Disconnect Switching and Method of Protecting Load Against Short Circuits
Patent: 6,031,702 →
Application: 08/956,257 →
Trench-Gated Power Mosfet with Protective Diode
Patent: 6,140,678 →
Application: 08/962,867 →
Method of Making Punch-Through Field Effect Transistor
Patent: 6,069,043 →
Application: 08/962,885 →
High Current, Low Profile Inductor
Patent: 6,204,744 →
Application: 08/963,224 →
High Density Trench Dmos Transistor with Trench Bottom Implant
Patent: 5,929,481 →
Application: 08/964,419 →
Method of Fabricating Vertical Power Mosfet Having Low Distributed Resistance
Patent: 6,043,125 →
Application: 08/966,553 →
Folded Ramp Capacitance Circuit with Current Source and Comparator Circuit
Patent: 5,955,903 →
Application: 08/979,837 →
Electrostatic Discharge Protection Circuit
Patent: 6,060,752 →
Application: 09/002,179 →
Portable Computer Containing Bidirectional Current Blocking Mosfet for Battery Disconnect Switching
Patent: 6,087,740 →
Application: 09/006,774 →
Pseudo-Schottky Diode
Patent: 6,476,442 →
Application: 09/037,557 →
Power Mosfet Including Internal Power Supply Circuitry
Patent: 6,087,862 →
Application: 09/041,368 →
Vertical Dmos Field Effect Transistor with Conformal Buried Layer for Reduced On-Resistance
Patent: 6,072,216 →
Application: 09/071,729 →
Multi-Tap Thin Film Inductor
Patent: 6,159,817 →
Application: 09/074,185 →
Thick Film Low Value High Frequency Inductor, and Method of Making the Same
Patent: 6,215,387 →
Application: 09/080,494 →
Vertical Trench-Gated Power Mosfet Having Stripe Geometry and High Cell Density
Patent: 6,204,533 →
Application: 09/089,250 →
Ic Chip Package with Directly Connected Leads
Patent: 6,249,041 →
Application: 09/089,310 →
Method of Forming Trench Power Mosfet
Patent: 6,096,608 →
Application: 09/186,216 →
Trench Mosfet Having Improved Breakdown and on-Resistance Characteristics
Patent: 6,084,264 →
Application: 09/200,197 →
Surface Mounted Four Terminal Resistor
Patent: 5,999,085 →
Application: 09/247,490 →
Method of Fabricating Lateral Power Mosfet Having Metal Strap Layer to Reduce Distributed Resistance
Patent: 6,159,841 →
Application: 09/264,602 →
Inductor Coil Structure
Patent: 6,198,375 →
Application: 09/271,748 →
Method of Forming Vertical Planar Dmosfet with Self-Aligned Contact
Patent: 6,277,695 →
Application: 09/293,380 →
Power Mosfet Having Voltage-Clamped Gate
Patent: 6,172,383 →
Application: 09/306,003 →
Method of Forming Vertical Mosfet Device Having Voltage-Clamped Gate and Self-Aligned Contact
Patent: 6,268,242 →
Application: 09/314,621 →
Chip Scale Surface Mount Packages for Semiconductor Device and Process of Fabricating the Same
Patent: 6,316,287 →
Application: 09/395,094 →
Process of Fabricating a Chip Scale Surface Mount Package for Semiconductor Device
Patent: 6,271,060 →
Application: 09/395,095 →
Rf Modem Utilizing Saw Resonator and Correlator and Communications Transceiver Constructed Therefrom
Patent: 6,535,545 →
Application: 09/419,824 →
High Density Trench-Gated Power Mosfet
Patent: 6,348,712 →
Application: 09/428,299 →
Surface Mount Resistor
Patent: 6,184,775 →
Application: 09/441,434 →
Thick Film Low Value High Frequency Inductor, and Method of Making the Same
Patent: 6,201,215 →
Application: 09/448,676 →
Semiconductor Die Package Including Cup-Shaped Leadframe
Patent: 6,744,124 →
Application: 09/468,249 →
Method for Making Formed Surface Mount Resistor
Patent: 6,510,605 →
Application: 09/471,617 →
Method for Making Overlay Surface Mount Resistor
Patent: 6,401,329 →
Application: 09/471,622 →
Monolithic Heat Sinking Resistor
Patent: 6,181,234 →
Application: 09/474,448 →
Barrier Accumulation Mode Mosfet
Patent: 6,285,060 →
Application: 09/476,320 →
Method of Operation of Punch-Through Field Effect Transistor
Patent: 6,444,527 →
Application: 09/481,135 →
Publication: US 2002/0055232
Method and Apparatus for Delivering Power Simultaneously to Rechargeable Battery and Electronic Device
Patent: 6,300,744 →
Application: 09/502,546 →
Vertical Structure and Process for Semiconductor Wafer-Level Chip Scale Packages
Patent: 6,392,290 →
Application: 09/545,287 →
Method for Making Inductor Coil Structure
Patent: 6,449,829 →
Application: 09/546,859 →
Method for Making a High Current Low Profile Inductor
Patent: 6,460,244 →
Application: 09/547,155 →
Surface Mounted Four Terminal Resistor
Patent: 39,660 →
Application: 09/568,937 →
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Patent: 6,538,300 →
Application: 09/661,483 →
Rf Modem and Communications Transceiver Utilizing Saw Device and Pulse Shaping
Patent: 6,970,496 →
Application: 09/688,300 →
Overlay Surface Mount Resistor
Patent: 6,441,718 →
Application: 09/715,252 →
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Patent: 6,441,475 →
Application: 09/733,823 →
Publication: US 2001/0000631
Method of Forming Termination on Chip Components
Patent: 6,541,302 →
Application: 09/758,800 →
Publication: US 2002/0090790
Fast Heat Rise Resistor Using Resistive Foil
Patent: 6,680,668 →
Application: 09/765,901 →
Publication: US 2002/0097137
Side-By-Side Coil Inductor
Patent: 6,587,025 →
Application: 09/774,854 →
Publication: US 2002/0101318
Method for Thin Film Ntc Thermistor
Patent: 6,880,234 →
Application: 09/810,206 →
Publication: US 2002/0130758
Power Chip Resistor
Patent: 7,038,572 →
Application: 09/811,844 →
Publication: US 2002/0130762
Method of Fabricating Trench-Gated Power Mosfet
Patent: 6,534,366 →
Application: 09/816,717 →
Publication: US 2001/0045598
Precision Resistor Tube Feeder
Patent: 6,669,435 →
Application: 09/820,064 →
Publication: US 2002/0141832
Method for Tantalum Pentoxide Moisture Barrier in Film Resistors
Patent: 7,214,295 →
Application: 09/829,169 →
Publication: US 2002/0145503
Structure of making a thick film low value high frequency inductor
Patent: 6,366,192 →
Application: 09/834,123 →
Publication: US 2001/0019298
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Patent: 6,562,647 →
Application: 09/844,934 →
Publication: US 2001/0016369
Process for Manufacturing Trench Gated Mosfet Having Drain/Drift Region
Patent: 6,569,738 →
Application: 09/898,652 →
Publication: US 2003/0006454
Novel Current Limiting Technique for Hybrid Power Mosfet Circuits
Patent: 6,552,889 →
Application: 09/908,178 →
Trench Mis Device with Active Trench Corners and Thick Bottom Oxide and Method of Making the Same
Patent: 6,849,898 →
Application: 09/927,143 →
Publication: US 2003/0032247
Trench Mis Device with Reduced Gate-to-Drain Capacitance
Patent: 6,882,000 →
Application: 09/927,320 →
Publication: US 2003/0030092
Leadframe Having Slots in a Die Pad
Patent: 6,744,119 →
Application: 09/978,603 →
Publication: US 2002/0056894
Surge Current Chip Resistor
Patent: 6,873,028 →
Application: 10/002,868 →
Publication: US 2003/0089964
Method for Making Overlay Surface Mount Resistor
Patent: 6,725,529 →
Application: 10/078,311 →
Publication: US 2002/0092154
Apparatus for Tantalum Pentoxide Moisture Barrier in Film Resistors
Patent: 7,170,389 →
Application: 10/079,010 →
Publication: US 2002/0145504
Method for Making a Resistor Using Resistive Foil
Patent: 6,671,945 →
Application: 10/079,085 →
Publication: US 2002/0097138
Method for Manufacturing a Power Chip Resistor
Patent: 6,859,999 →
Application: 10/091,792 →
Publication: US 2002/0130760
Method of Making Trench-Gated Mosfet Having Cesium Gate Oxide Layer
Patent: 6,509,233 →
Application: 10/094,476 →
Publication: US 2002/0123196
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent: 6,838,722 →
Application: 10/104,811 →
Publication: US 2003/0178673
Trench Mis Device with Graduated Gate Oxide Layer
Patent: 6,903,412 →
Application: 10/106,812 →
Publication: US 2003/0030104
Method of Fabricating Trench Mis Device with Graduated Gate Oxide Layer
Patent: 6,875,657 →
Application: 10/106,896 →
Publication: US 2003/0032248
Encapsulation Method and Leadframe for Leadless Semiconductor Packages
Patent: 6,856,006 →
Application: 10/113,526 →
Publication: US 2003/0183910
Method of Fabricating Trench Junction Barrier Rectifier
Patent: 7,186,609 →
Application: 10/146,539 →
Publication: US 2002/0125541
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Patent: 6,876,061 →
Application: 10/157,584 →
Publication: US 2002/0185710
Thicker Oxide Formation at the Trench Bottom by Selective Oxide Deposition
Patent: 6,709,930 →
Application: 10/176,570 →
Publication: US 2003/0235958
Self-Aligned Differential Oxidation in Trenches by Ion Implantation
Patent: 7,012,005 →
Application: 10/180,154 →
Publication: US 2003/0235959
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Patent: 6,621,142 →
Application: 10/208,121 →
Publication: US 2003/0057517
Precision High-Frequency Capacitor on Semiconductor Substrate
Patent: 6,621,143 →
Application: 10/208,599 →
Publication: US 2003/0030125
Trench Mosfet Having Implanted Drain-Drift Region
Patent: 6,600,193 →
Application: 10/211,438 →
Publication: US 2003/0008460
Flip Chip Resistor and Its Manufacturing Method
Patent: 6,727,798 →
Application: 10/233,184 →
Publication: US 2004/0041688
Inductor Coil and Method for Making Same
Patent: 6,946,944 →
Application: 10/244,777 →
Publication: US 2003/0016114
Semiconductor Substrate with Trenches for Reducing Substrate Resistance
Patent: 6,858,471 →
Application: 10/247,906 →
Method of Forming Self Aligned Contacts for a Power Mosfet
Patent: 8,629,019 →
Application: 10/254,385 →
Publication: US 2004/0058481
Method for Making Trench Mis Device with Reduced Gate-to-Drain Capacitance
Patent: 6,921,697 →
Application: 10/264,816 →
Publication: US 2003/0062570
Semiconductor Assembly with Package Using Cup-Shaped Lead Frame
Patent: 6,909,170 →
Application: 10/291,153 →
Publication: US 2003/0057532
Method of Manufacturing a Resistor
Patent: 6,892,443 →
Application: 10/304,261 →
Publication: US 2004/0100356
Method for Making Trench Mosfet Having Implanted Drain-Drift Region
Patent: 6,764,906 →
Application: 10/317,568 →
Publication: US 2003/0102564
Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide and Process for Manufacturing the Same
Patent: 7,033,876 →
Application: 10/326,311 →
Publication: US 2004/0121572
Method of Forming Self Aligned Contacts for a Power Mosfet
Patent: 8,367,500 →
Application: 10/378,766 →
Method of Manufacturing Flip Chip Resistor
Patent: 7,089,652 →
Application: 10/440,941 →
Publication: US 2004/0041278
High Power Resistor Having an Improved Operating Temperature Range
Patent: 7,102,484 →
Application: 10/441,649 →
Publication: US 2004/0233032
Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide
Patent: 7,291,884 →
Application: 10/454,031 →
Publication: US 2004/0038467
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Patent: 7,151,036 →
Application: 10/456,018 →
Triple-Diffused Trench Mosfet and Method of Fabricating the Same
Patent: 6,913,977 →
Application: 10/657,830 →
Publication: US 2005/0054177
Trench Mis Device with Thick Oxide Layer in Bottom of Gate Contact Trench
Patent: 7,009,247 →
Application: 10/722,984 →
Publication: US 2004/0166636
Closed Cell Trench Metal-Oxide-Semiconductor Field Effect Transistor
Patent: 7,279,743 →
Application: 10/726,922 →
Publication: US 2005/0116282
Method for Making High Power Resistor Having Improved Operating Temperature Range
Patent: 6,925,704 →
Application: 10/744,846 →
High Precision Power Resistors
Patent: 7,154,370 →
Application: 10/762,609 →
Publication: US 2004/0150505
Encapsulation Method for Leadless Semiconductor Packages
Patent: 7,501,086 →
Application: 10/789,799 →
Publication: US 2004/0169316
Surface Mount Flipchip Capacitor
Patent: 6,914,770 →
Application: 10/792,135 →
Surface Mount Melf Capacitor
Patent: 7,088,573 →
Application: 10/792,138 →
Publication: US 2005/0195553
Surface Mount Chip Capacitor
Patent: 7,085,127 →
Application: 10/792,639 →
Publication: US 2005/0195558
Method for Making Overlay Surface Mount Resistor
Patent: 6,901,655 →
Application: 10/797,866 →
Publication: US 2004/0168304
Termination for Trench Mis Device Having Implanted Drain-Drift Region
Patent: 7,045,857 →
Application: 10/810,031 →
Publication: US 2005/0215011
Termination for Trench Mis Device Having Implanted Drain-Drift Region
Patent: 6,927,451 →
Application: 10/811,443 →
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent: 7,005,347 →
Application: 10/832,776 →
Super Trench Mosfet Including Buried Source Electrode and Method of Fabricating the Same
Patent: 7,183,610 →
Application: 10/836,833 →
Publication: US 2005/0242392
Drain Side Gate Trench Metal-Oxide-Semiconductor Field Effect Transistor
Patent: 6,906,380 →
Application: 10/846,339 →
Self Aligned Contact in a Semiconductor Device and Method of Fabricating the Same
Patent: 8,080,459 →
Application: 10/869,382 →
Publication: US 2005/0224891
Process for Manufacturing Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide
Patent: 7,435,650 →
Application: 10/872,931 →
Publication: US 2004/0227182
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent: 7,335,946 →
Application: 10/898,431 →
Method of Forming Self Aligned Contacts for a Power Mosfet
Patent: 7,642,164 →
Application: 10/951,831 →
Method for Manufacturing a Fast Heat Rise Resistor
Patent: 7,247,250 →
Application: 10/964,357 →
Publication: US 2005/0224454
Method of Manufacturing a Resistor
Patent: 7,278,201 →
Application: 10/967,883 →
Publication: US 2005/0083170
Semiconductor Package Including Die Interposed Between Cup-Shaped Lead Frame and Lead Frame Having Mesas and Valleys
Patent: 7,394,150 →
Application: 10/996,148 →
Publication: US 2006/0108671
Method of Fabricating Semiconductor Package Including Die Interposed Between Cup-Shaped Lead Frame Having Mesas and Valleys
Patent: 7,238,551 →
Application: 10/996,149 →
Publication: US 2006/0110856
Method of Manufacturing a Drain Side Gate Trench Metal-Oxide-Semiconductor Field Effect Transistor
Patent: 7,344,945 →
Application: 11/023,327 →
Inductor Coil and Method for Making Same
Patent: 7,034,645 →
Application: 11/038,880 →
Publication: US 2005/0122200
Method of Manufacturing a Closed Cell Trench Mosfet
Patent: 7,361,558 →
Application: 11/040,129 →
Publication: US 2005/0148128
Method for Interwoven Spreading Codes
Patent: 7,394,845 →
Application: 11/050,077 →
Publication: US 2006/0171447
Surface Mount Electrical Resistor with Thermally Conductive, Electrically Insulative Filler and Method for Using Same
Patent: 7,190,252 →
Application: 11/066,865 →
Publication: US 2006/0197648
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Patent: 7,211,877 →
Application: 11/082,080 →
Trench-Gated Mis Device Having Thick Polysilicon Insulation Layer at Trench Bottom and Method of Fabricating the Same
Patent: 7,494,876 →
Application: 11/112,403 →
High Power Resistor Having an Improved Operating Temperature Range
Patent: 7,042,328 →
Application: 11/123,508 →
Publication: US 2005/0212649
Surface Mount Capacitor and Method of Making Same
Patent: 7,161,797 →
Application: 11/132,116 →
Publication: US 2006/0262489
Process of Fabricating Termination Region for Trench Mis Device
Patent: 7,118,953 →
Application: 11/141,942 →
Publication: US 2005/0218447
Triple-Diffused Trench Mosfet
Patent: 7,233,043 →
Application: 11/150,016 →
Publication: US 2005/0280077
Semiconductor Die Package Including Cup-Shaped Leadframe
Patent: 7,595,547 →
Application: 11/151,749 →
Trench Mis Device Having Implanted Drain-Drift Region and Thick Bottom Oxide
Patent: 7,326,995 →
Application: 11/158,382 →
Publication: US 2005/0236665
Electrostatic Discharge Protection Circuit for Integrated Circuits
Patent: 7,583,485 →
Application: 11/190,682 →
Termination for Trench Mis Device Having Implanted Drain-Drift Region
Patent: 7,268,032 →
Application: 11/232,613 →
Publication: US 2006/0019448
Surface Mount Melf Capacitor
Patent: 7,167,357 →
Application: 11/259,503 →
Publication: US 2006/0104007
Surface Mount Melf Capacitor
Patent: 7,221,555 →
Application: 11/264,977 →
Publication: US 2006/0056134
Surface Mount Chip Capacitor
Patent: 7,179,309 →
Application: 11/266,632 →
Publication: US 2006/0061939
Method of Maufacturing Surface Mount Capacitor
Patent: 7,449,032 →
Application: 11/266,915 →
Publication: US 2006/0260109
Surface Mount Chip Capacitor
Patent: 7,283,350 →
Application: 11/293,673 →
Publication: US 2007/0127189
Trench Polysilicon Diode
Patent: 7,544,545 →
Application: 11/322,040 →
Publication: US 2007/0145411
Method of Fabricating Trench Mis Device with Thick Oxide Layer in Bottom of Trench
Patent: 7,416,947 →
Application: 11/335,747 →
Publication: US 2006/0121676
Adaptive Frequency Compensation for Dc-to-Dc Converter
Patent: 7,880,446 →
Application: 11/352,031 →
Publication: US 2006/0176098
High Voltage Capacitors
Patent: 7,336,475 →
Application: 11/359,711 →
Publication: US 2007/0195484
Narrow Semiconductor Trench Structure
Patent: 9,685,524 →
Application: 11/373,630 →
Publication: US 2007/0048966
Flux Channeled, High Current Inductor
Patent: 7,864,015 →
Application: 11/380,293 →
Publication: US 2007/0252669
Ultra-Low Drain-Source Resistance Power Mosfet
Patent: 8,409,954 →
Application: 11/386,927 →
Publication: US 2007/0221989
Inductor Coil
Patent: 7,221,249 →
Application: 11/409,651 →
Publication: US 2006/0186980
High Precision Capacitor with Standoff
Patent: 7,426,102 →
Application: 11/415,039 →
Publication: US 2007/0253143
Complete Power Management System Implemented in a Single Surface Mount Package
Patent: 9,093,359 →
Application: 11/479,619 →
Publication: US 2007/0063340
Complete Power Management System Implemented in a Single Surface Mount Package
Patent: 8,471,381 →
Application: 11/479,671 →
Publication: US 2007/0063341
Inductor with Thermally Stable Resistance
Patent: 8,018,310 →
Application: 11/535,758 →
Publication: US 2008/0074225
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Patent: 8,004,063 →
Application: 11/601,501 →
Publication: US 2010/0295152
Method for Making a High Current Low Profile Inductor
Patent: 7,263,761 →
Application: 11/609,165 →
Publication: US 2007/0186407
High Mobility Power Metal-Oxide Semiconductor Field-Effect Transistors
Patent: 9,425,043 →
Application: 11/644,553 →
Publication: US 2007/0262360
High-Density Power Mosfet with Planarized Metalization
Patent: 9,437,729 →
Application: 11/651,258 →
Publication: US 2008/0164515
Floating Gate Structure with High Electrostatic Discharge Performance
Patent: 9,111,754 →
Application: 11/655,493 →
Publication: US 2007/0236843
Super Trench Mosfet Including Buried Source Electrode
Patent: 7,557,409 →
Application: 11/698,519 →
Publication: US 2007/0187753
Process for Forming a Short Channel Trench Mosfet and Device Formed Thereby
Patent: 8,883,595 →
Application: 11/710,041 →
Publication: US 2008/0012068
Ceramic Dielectric Formulation for Broad Band Uhf Antenna
Patent: 7,907,090 →
Application: 11/759,523 →
Publication: US 2008/0303720
Method for Making a High Current Low Profile Inductor
Patent: 7,345,562 →
Application: 11/782,020 →
Publication: US 2007/0262841
Chip Scale Surface Mount Package for Semiconductor Device and Process of Fabricating the Same
Patent: 7,589,396 →
Application: 11/786,328 →
Publication: US 2007/0235774
Power Mosfet Contact Metallization
Patent: 8,471,390 →
Application: 11/799,889 →
Publication: US 2007/0284754
Current Mode Boost Converter Using Slope Compensation
Patent: 8,222,874 →
Application: 11/823,375 →
Publication: US 2009/0001943
Power Resistor
Patent: 7,843,309 →
Application: 11/862,572 →
Publication: US 2009/0085715
Precision High-Frequency Capacitor Formed on Semiconductor Substrate
Patent: 9,136,060 →
Application: 11/966,965 →
Publication: US 2008/0108202
Structures of and Methods of Fabricating Trench-Gated Mis Devices
Patent: 7,868,381 →
Application: 11/982,906 →
Trench Polysilicon Diode
Patent: 7,612,431 →
Application: 12/009,379 →
Publication: US 2008/0135872
Method for Making a High Current Low Profile Inductor
Patent: 7,921,546 →
Application: 12/013,725 →
Publication: US 2008/0110014
Self-Aligned Trench Mosfet and Method of Manufacture
Patent: 9,947,770 →
Application: 12/015,723 →
Publication: US 2008/0246081
Resistor, and Method for Making Same
Patent: 7,911,319 →
Application: 12/026,939 →
Publication: US 2009/0195348
Sulfuration Resistant Chip Resistor and Method for Making Same
Patent: 7,982,582 →
Application: 12/030,281 →
Publication: US 2008/0211619
Self-Repairing Field Effect Transistor
Application: 12/030,719 →
Publication: US 2009/0200578
Narrow Semiconductor Trench Structure
Patent: 9,412,833 →
Application: 12/030,809 →
Publication: US 2009/0104751
Surface Mounted Chip Resistor with Flexible Leads
Patent: 7,965,169 →
Application: 12/035,472 →
Publication: US 2009/0212900
Stacked Trench Metal-Oxide-Semiconductor Field Effect Transistor Device
Patent: 8,183,629 →
Application: 12/050,929 →
Publication: US 2009/0050960
Electrophoretically Deposited Cathode Capacitor
Patent: 9,070,512 →
Application: 12/052,251 →
Publication: US 2009/0237863
Ultra-low drain-source resistance power MOSFET
Patent: 9,887,266 →
Application: 12/069,712 →
Publication: US 2008/0157281
Trench Metal Oxide Semiconductor with Recessed Trench Material and Remote Contacts
Patent: 8,368,126 →
Application: 12/098,950 →
Publication: US 2008/0258212
A Method of Making a Frame Package Array Device
Patent: 8,028,397 →
Application: 12/107,349 →
Publication: US 2008/0189931
Method of Manufacturing a Closed Cell Trench Mosfet
Patent: 7,833,863 →
Application: 12/107,738 →
Highly Coupled Inductor
Patent: 7,936,244 →
Application: 12/114,057 →
Publication: US 2009/0273432
High Current Density Power Field Effect Transistor
Patent: 8,269,263 →
Application: 12/119,367 →
Publication: US 2009/0278176
High Mobility Power Metal-Oxide Semiconductor Field-Effect Transistors
Patent: 9,437,424 →
Application: 12/123,664 →
Publication: US 2008/0220571
High Powered Inductors Using a Magnetic Bias
Patent: 8,004,379 →
Application: 12/134,240 →
Publication: US 2009/0066454
High Voltage Capacitors
Patent: 8,125,762 →
Application: 12/189,465 →
Publication: US 2010/0033894
High Voltage Capacitors
Patent: 8,238,075 →
Application: 12/189,492 →
Publication: US 2009/0052111
Mosfet Active Area and Edge Termination Area Charge Balance
Patent: 9,484,451 →
Application: 12/203,846 →
Publication: US 2009/0090967
Resistor and Method for Making Same
Patent: 8,242,878 →
Application: 12/205,197 →
Publication: US 2010/0060409
Encapsulation Techniques for Leadless Semiconductor Packages
Patent: 8,928,157 →
Application: 12/401,549 →
Publication: US 2009/0174055
Semiconductor Including Cup-Shaped Leadframe Packaging Techniques
Patent: 9,040,356 →
Application: 12/487,666 →
Publication: US 2009/0256246
Method for Making a High Current Low Profile Inductor
Patent: 7,986,207 →
Application: 12/535,757 →
Publication: US 2010/0007455
Metal Strip Resistor for Mitigating Effects of Thermal Emf
Patent: 8,248,202 →
Application: 12/536,792 →
Publication: US 2010/0237982
Super Junction Trench Power Mosfet Devices
Patent: 9,425,306 →
Application: 12/548,841 →
Publication: US 2011/0049614
Super Junction Trench Power Mosfet Device Fabrication
Patent: 9,443,974 →
Application: 12/549,190 →
Publication: US 2011/0053326
Electrostatic Discharge Protection Circuit for Integrated Circuits
Patent: 8,582,258 →
Application: 12/552,205 →
Bulk Capacitor and Method
Patent: 8,238,076 →
Application: 12/553,508 →
Publication: US 2010/0073846
Adaptive Frequency Compensation for Dc-to-Dc Converter
Patent: 7,960,947 →
Application: 12/571,194 →
Publication: US 2010/0019751
Split Gate Semiconductor Device with Curved Gate Oxide Profile
Patent: 9,419,129 →
Application: 12/603,028 →
Publication: US 2011/0089485
Semiconductor Device with Trench-Like Feed-Throughs
Patent: 9,306,056 →
Application: 12/610,148 →
Publication: US 2011/0101525
Trench Polysilicon Diode
Patent: 8,072,013 →
Application: 12/611,865 →
Surface Mount Resistor with Terminals for High-Power Dissipation and Method for Making Same
Patent: 8,325,007 →
Application: 12/650,079 →
Publication: US 2011/0156860
Semiconductor Packages Including Die and L-Shaped Lead and Method of Manufacture
Patent: 8,586,419 →
Application: 12/730,230 →
Publication: US 2011/0175217
Hermetically Sealed Wet Electrolytic Capacitor
Application: 12/759,769 →
Publication: US 2010/0268292
Complete Power Management System Implemented in a Single Surface Mount Package
Patent: 8,928,138 →
Application: 12/779,815 →
Publication: US 2010/0219519
Super-High Density Trench Mosfet
Patent: 9,431,530 →
Application: 12/788,158 →
Publication: US 2011/0089486
Field Boosted Metal-Oxide-Semiconductor Field Effect Transistor
Application: 12/824,075 →
Publication: US 2011/0095359
Power Switch with Active Snubber
Patent: 8,735,992 →
Application: 12/829,247 →
Publication: US 2011/0198704
Structures of and Methods of Fabricating Split Gate Mis Devices
Patent: 9,425,305 →
Application: 12/869,554 →
Publication: US 2011/0210406
System and Method for Substrate Wafer Back Side and Edge Cross Section Seals
Patent: 9,230,810 →
Application: 12/873,147 →
Publication: US 2011/0049682
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Patent: 8,198,977 →
Application: 12/874,514 →
Publication: US 2011/0057764
Semiconductor Chip Package
Patent: 466,873 →
Application: 29/151,024 →
Semiconductor Chip Package
Patent: 472,528 →
Application: 29/151,069 →
Transistor Structure with Feed-Through Source-to-Substrate Contact
Application: 61/257,362 →
Surface Mount Resistor with Terminals for High-Power Dissipation and Method for Making Same
Application: 61/290,429 →
Structures of and Methods of Fabricating Dual Gate Mis Devices
Application: 61/309,824 →
Resistor with Temperature Coefficient of Resistance (Tcr) Compensation
Application: 61/359,000 →
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement Mar 2, 2010
From: VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC; VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED
To: COMERICA BANK, AS AGENT
Reel/Frame 024006/0515 →
Release of Security Interest Dec 14, 2010
From: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
To: VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION; VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION; VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION; SILICONIX INCORPORATED, A DELAWARE CORPORATION
Reel/Frame 025489/0184 →
Security Interest Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
Release of Security Interest Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED
Reel/Frame 049826/0312 →