IP Library Granted Patent US 9,685,524
Granted Patent B2
US 9,685,524 · App. 11/373,630 · Granted Jun 20, 2017

Narrow semiconductor trench structure

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Quick Facts
Patent No.
US 9,685,524
App. No.
11/373,630
Granted
Jun 20, 2017
Kind
B2
Abstract

Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

Claims (12)

1. A semiconductor device comprising:

a substrate having a substrate top surface,

a void within said substrate,

wherein said substrate surrounds said void on the sides and bottom of said void;

a region of epitaxial material formed on said bottom of said void and having a top surface substantially planar with said substrate top surface; and

a trench having said substrate on one side and said epitaxial material on the other side,

wherein said trench is characterized as having a width dimension of less than one hundredth of the critical dimension of the semiconductor process used to manufacture said semiconductor device,

wherein epitaxial material is disposed only on one side of said trench,

wherein said critical dimension is 1.0 micron;

wherein said epitaxial material is of opposite carrier type of the substrate; and

further comprising a vertical channel adjacent to said trench.

2. The semiconductor device of claim 1 wherein said trench is characterized as having a width dimension of less than one thousandth of the critical dimension of the semiconductor process used to manufacture said semiconductor device.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED
Reel/Frame 049785/0771 →
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Sep 5, 2013
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 031170/0001 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2006
From: CHAU, THE-TU; LE, HOANG; CHEN, KUO-IN
To: VISHAY-SILICONIX
Reel/Frame 018508/0335 →