Process of fabricating termination region for trench MIS device
View Patent ↗A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.
1. A process of fabricating a termination region for a trench MIS device comprising:
providing a semiconductor wafer, said wafer comprising a first layer of a first conductivity type and a second layer of a second conductivity type overlying said first layer;
forming a first trench in said wafer, said first trench coinciding with a scribe line bordering a die of said wafer, a bottom of said first trench being located in said second layer;
introducing a dopant of said first conductivity type through a bottom of said first trench to form a region of said first conductivity type extending from said bottom of said first trench to said first layer;
forming an insulating layer in said first trench and over a surface of said layer of second conductivity type;
forming a termination metal layer over said insulating layer in said first trench and over said surface of said layer of second conductivity type;
etching an opening in said metal layer at a bottom of said first trench, said scribe line intersecting said opening; and
sawing said wafer at said scribe line.
2. The process of claim 1 comprising a forming a second trench in an active area of said die while forming said first trench, a bottom of said second trench being located in said second layer.
3. The process of claim 2 comprising introducing a dopant of said first conductivity type through a bottom of said second trench while introducing a dopant of said first conductivity type through a bottom of said first trench to form a drain-drift region of said first conductivity type extending from said bottom of said second trench to said first layer.
4. The process of claim 3 comprising forming a source region of said first conductivity type adjacent said second trench and said surface of said second layer.
5. The process of claim 4 comprising introducing a conductive material into said second trench to form a gate.
6. The process of claim 5 wherein forming said insulating layer comprises depositing an insulating layer that overlies said gate and extends into said first trench.
7. The process of claim 6 comprising forming a source metal layer over said surface of said second layer, said source metal layer being in electrical contact with said source region.
8. The process of claim 7 wherein said source metal layer extends into said first trench but does not extend to said scribe line.
9. The process of claim 8 wherein said source metal layer overlies a junction of said region of first conductivity type.
10. The process of claim 7 comprising forming an opening in said insulating layer at a bottom of said first trench.
11. The process of claim 10 comprising patterning said source metal layer so as to form an edge segment, said edge segment bordering said scribe line and being electrically isolated from a remaining portion of said source metal layer, said edge segment extending into said opening in said insulating layer to make electrical contact with said region of first conductivity type.
12. The process of claim 11 comprising forming a heavily-doped region of said first conductivity type within said region of first conductivity type, said edge segment being in electrical contact with said heavily-doped region of first conductivity type.