IP Library › Granted Patent US 7,089,652
Granted Patent B2
US 7,089,652 · App. 10/440,941 · Granted Aug 15, 2006

Method of manufacturing flip chip resistor

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Quick Facts
Patent No.
US 7,089,652
App. No.
10/440,941
Granted
Aug 15, 2006
Kind
B2
Abstract

The present invention provides for a method for manufacturing flip chip resistors by applying a first electrode layer to a substrate to create at least one pair of opposite electrodes, applying a resistance layer between each pair of opposite electrodes, applying a first protective layer at least partially overlaying the resistance layer, applying a second protective layer at least partially overlaying at least a portion of the resistance layer, and applying a second electrode layer overlaying the first electrode layer, a portion of the resistance layer, and at least a portion of the second protective layer. The present invention provides for higher reliability performance and enlarging the potential soldering area despite small chip size.

Claims (27)

1. A method of manufacturing flip chip resistors, comprising:

applying a first electrode layer to a top surface of a substrate to create at least one pair of opposite first electrodes;

applying a resistance layer between each pair of opposite first electrodes;

applying a first protective layer at least partially overlaying the resistance layer;

applying a second protective layer at least partially overlaying at least a portion of the resistance layer, the second protective layer having a top surface;

applying a second electrode layer overlaying and in contact with the first electrode layer, the second electrode layer extending inwardly to directly overlay a portion of the resistance layer, and the second electrode layer overlaying and in contact with a portion of the top surface of the second protective layer to form at least one pair of opposite second electrodes corresponding to the at least one pair of opposite first electrodes; and

wherein an innermost junction between the second protective layer and each of the second electrodes is positioned inward of the first corresponding electrode.

2. The method of claim 1 further comprising dividing the substrate into individual flip chip resistors.

3. The method of claim 1 further comprising trimming the resistance of the resistance layer.

4. The method of claim 1 further comprising plating the second electrode layer of each flip chip resistor, the plating extending over a portion of the top surface of the second protective layer.

5. The method of claim 1 wherein the substrate is an unscored sheet-shaped substrate and the step of dividing is performed by dicing.

6. The method of claim 1 wherein the substrate is an unscored sheet-shaped substrate and the step of dividing is performed by laser scribing.

7. A method of manufacturing flip chip resistors to provide flip chip resistors with pad areas which are sizeable independently from a resistance layer, comprising:

applying a first electrode layer to a top surface of a substrate to create at least one pair of opposite electrodes;

applying the resistance layer between each pair of opposite electrodes;

applying the first protective layer at least partially overlaying the resistance layer;

applying a second protective layer having a top surface and at least partially overlaying at least a portion of the resistance layer;

applying a second electrode layer directly overlaying and in contact with the first electrode layer, directly overlaying a portion of the resistance layer, and directly overlaying and in contact with a portion of the top surface of the second protective layer, the second electrode layer extending inwardly beyond the first electrode layer;

plating the second electrode layer to provide the pad areas such that size of the pad areas is independent of size of the resistance layer; and

wherein an innermost junction between the second protective layer and the second electrode layer is positioned inward of the first electrode.

8. A method of manufacturing a flip chip resistor, comprising:

applying a first electrode layer to a top surface of a substrate to create at least one pair of opposite electrodes;

applying the resistance layer between each pair of opposite electrodes;

applying a first protective layer at least partially overlaying the resistance layer;

applying a second protective layer having a top surface and at least partially overlaying at least a portion of the resistance layer;

applying a second electrode layer which overlays and contacts the first electrode layer, and directly overlays a portion of the resistance layer and directly overlays and contacts a portion of the top surface of the second protective layer to form at least one pair of opposite second electrodes; and

wherein a portion of each of the second electrodes extends inwardly beyond the corresponding first electrode and inwardly beyond and directly over the resistance layer.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
RELEASE OF SECURITY INTEREST Recorded Dec 14, 2010
From: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
To: VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION; VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION; VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION; SILICONIX INCORPORATED, A DELAWARE CORPORATION; VISHAY MEASUREMENTS GROUP, INC., A DELAWARE CORPORATION; VISHAY GENERAL SEMICONDUCTOR, LLC, F/K/A GENERAL SEMICONDUCTOR, INC., A DELAWARE LIMITED LIABILITY COMPANY; VISHAY VITRAMON, INCORPORATED, A DELAWARE CORPORATION; YOSEMITE INVESTMENT, INC., AN INDIANA CORPORATION
Reel/Frame 025489/0184 →
SECURITY AGREEMENT Recorded Mar 2, 2010
From: VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC; VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY MEASUREMENTS GROUP, INC.
To: COMERICA BANK, AS AGENT
Reel/Frame 024006/0515 →