IP Library Granted Patent US 9,412,833
Granted Patent B2
US 9,412,833 · App. 12/030,809 · Granted Aug 9, 2016

Narrow semiconductor trench structure

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Quick Facts
Patent No.
US 9,412,833
App. No.
12/030,809
Granted
Aug 9, 2016
Kind
B2
Abstract

Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

Claims (14)

1. A semiconductor fabrication method for forming a narrow trench, said method comprising:

forming a first layer of insulating material on a substrate;

creating a trench through the first layer of insulating material and into the substrate;

forming a second insulating material on the first layer and on exposed portions of the trench;

removing the second insulating material from the first layer of insulating material and the bottom of the trench;

filling the trench with an epitaxial material;

removing the first layer of insulating material; and

forming a narrow trench by the removal of remaining portions of the second insulating material.

2. The method of claim 1 wherein said forming a first layer of insulating material comprises growing said first layer of insulating material.

3. The method of claim 1 wherein said forming a second insulating material comprises growing said second insulating material.

4. The method of claim 1 wherein said removing the second insulating material comprises applying a blanket dry etching process.

5. The method of claim 1 wherein said filling comprises growing epitaxial material.

6. The method of claim 1 wherein said removing the first layer of insulating material comprises applying chemical mechanical polishing.

7. The method of claim 1 further comprising annealing the substrate at high temperature in a Hydrogen-ambient atmosphere.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →