Method of fabricating trench MIS device with graduated gate oxide layer
View Patent ↗A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.
1. A method of fabricating an MIS device comprising:
providing a semiconductor substrate;
forming a trench in said substrate;
depositing a nitride layer in said trench;
etching said nitride layer to form an exposed area at a bottom of said trench; said etching exposing a lateral surface of said nitride layer on each side of said exposed area;
heating the substrate and thereby growing an oxide layer in said exposed area, said oxide layer abutting said lateral surface of said nitride layer on each side of said exposed area;
removing said nitride layer;
forming a relatively thin gate oxide layer on at least a portion of a sidewall of said trench; and
forming a gate in said trench.
2. The method of claim 2 , wherein forming a gate comprises:
depositing doped polysilicon in said trench; and
etching said doped polysilicon to a level about equal to a surface of said substrate.
3. A method of fabricating an MIS device comprising:
providing a semiconductor substrate;
forming a trench in said substrate;
depositing a nitride layer in said trench;
etching said nitride layer to form an exposed area at a bottom of said trench;
heating the substrate and thereby growing an oxide layer in said exposed area;
removing a portion of said nitride layer;
oxidizing a remaining portion of said nitride layer to form oxidized nitride;
removing said oxidized nitride
forming a relatively thin gate oxide layer on at least a portion of a sidewall of said trench; and
forming a gate in said trench.
4. The method of claim 1 wherein growing an oxide layer comprises causing a portion of said nitride layer to lift oft from a surface of said trench.
5. The method of claim 1 wherein depositing a nitride layer comprises depositing a nitride layer 500 Å or less thick.
6. The method of claim 1 wherein depositing a nitride layer comprises depositing a nitride layer in the range of 1,500 to 2,000 Å thick.
7. The method of claim 1 wherein growing an oxide layer comprises creating a transition region wherein a thickness of the oxide layer gradually decreases in a direction away form said exposed area.
8. The method of claim 7 wherein the substrate is of a first conductivity type, the method further comprising diffusing dopant of a second conductivity type into said substrate, said dopant forming a PN junction with a remaining portion of said substrate.
9. A method of fabricating an MIS device comprising:
providing a semiconductor substrate of a first conductivity type;
forming a trench in said substrate;
depositing a nitride layer in said trench;
etching said nitride layer to form an exposed area at a bottom of said trench;
heating the substrate and thereby growing an oxide layer in said exposed area, thereby creating a transition region wherein a thickness of the oxide layer gradually decreases in a direction away form said exposed area; and
diffusing dopant of a second conductivity type into said substrate, said dopant forming a PN junction with a remaining portion of said substrate;
wherein diffusing dopant of said second conductivity type comprises controlling the diffusion of said PN junction such that said PN junction intersects the trench in said transition region.
10. The method of claim 1 comprising implanting dopant through a bottom of said trench to form a heavily doped region adjacent said bottom of said trench.
11. The method of claim 1 wherein etching said nitride layer comprises a directional etch.
12. The method of claim 1 wherein etching said nitride layer comprises a directional, dry plasma etch.
13. The method of claim 1 wherein etching said nitride layer comprises a reactive ion etch.
14. The method of claim 1 wherein said etching said nitride layer leaves a remaining section of said nitride layer covering a corner area of said trench.