Precision high-frequency capacitor formed on semiconductor substrate
A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.
1. A method of fabricating a capacitor in a semiconductor substrate having a first principal surface and a second principal surface, said method comprising:
forming a dielectric layer on the first principal surface of the semiconductor substrate;
forming an electrical conductive layer on the second principal surface of the semiconductor substrate such that the electrical conductive layer makes contact with the second principal surface;
cutting a via through the semiconductor substrate from the first principal surface to the second principal surface;
depositing an electrical conductive material into the via;
forming an electrode layer comprising a first portion and a second portion, the first portion being insulated from the semiconductor substrate by the dielectric layer, the second portion being in electrical contact with the electrical conductive material in the via, wherein said first portion operates as a first plate of said capacitor and wherein said semiconductor substrate operates as a second plate of said capacitor.
2. The method as recited in claim 1 wherein the doping concentration of the semiconductor substrate is greater than 1×10 19 cm −3 .
3. The method as recited in claim 1 wherein the thickness of said semiconductor substrate is less than 200 microns.
4. The method as recited in claim 1 wherein the dielectric layer comprises an oxide.
5. The method as recited in claim 1 wherein the thickness of the dielectric layer is greater than or equal to 0.005 micron.
6. The method as recited in claim 1 further comprising forming a passivation layer overlying the first portion and the second portion, a first opening being formed in the passivation layer over the first portion and a second opening being formed in the passivation layer over the second portion.
7. The method as recited in claim 6 further comprising forming a first metal ball in the first opening and a second metal ball in the second opening, the first metal ball being electrically connected to the first portion, the second metal ball being electrically connected to the second portion.