Precision high-frequency capacitor formed on semiconductor substrate
View Patent ↗A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
1. A method of fabricating a capacitor in a semiconductor substrate comprising a first surface and a second surface, said method comprising:
forming a first dielectric layer directly on a first portion of said first surface of said semiconductor substrate;
forming a first electrode layer directly over said first dielectric layer, wherein said first electrode layer is electrically insulated from said semiconductor substrate;
forming a second dielectric layer directly on a second portion of said first surface of said semiconductor substrate, wherein said first dielectric layer is separated from said second dielectric layer;
forming a second electrode layer directly over said second dielectric layer, wherein said first electrode, said second electrode, said first dielectric layer and said second dielectric layer form a plurality of capacitors in series, and wherein said first and said second electrode layers comprise a plurality of fingers, and wherein a first portion of said first electrode layer is interdigitated with a second portion of said second electrode layer.
2. The method as described in claim 1 , wherein the doping concentration of said semiconductor substrate is greater than 1×10 19 cm −3 .
3. The method as described in claim 1 , wherein the thickness of said semiconductor substrate is less than 200 microns.
4. The method as described in claim 1 , wherein the first dielectric layer comprises an oxide.
5. The method as described in claim 1 , wherein the thickness of said first dielectric layer is greater than or equal to 0.005 microns.
6. The method as described in claim 1 further comprising:
forming a passivation layer overlying said first electrode and said second electrode wherein a first opening is formed in said passivation layer over said first electrode and a second opening is formed in the passivation layer over said second electrode.
7. The method as described in claim 6 further comprising:
forming a first metal ball in said first opening, wherein said first metal ball is electrically coupled to said first electrode; and
forming a second metal ball in said second opening, wherein said second metal ball is electrically coupled to said second electrode.
8. The method as described in claim 1 further comprising:
forming at least one trench under said first electrode and said second electrode, and wherein a portion of said first dielectric covers a sidewall of said at least one trench.
9. A capacitor comprising:
a first dielectric layer formed directly on a first portion of said first surface of said semiconductor substrate;
a first electrode layer formed directly over said first dielectric layer, wherein said first electrode layer is electrically insulated from said semiconductor substrate;
a second dielectric layer formed directly on a second portion of said first surface of said semiconductor substrate, wherein said first dielectric layer is separated from said second dielectric layer; and
a second electrode layer formed directly over said second dielectric layer, wherein said first electrode, said second electrode, said first dielectric layer and said second dielectric layer form a plurality of capacitors in series, and wherein said first and said second electrode layers comprise a plurality of fingers, and wherein a first portion of said first electrode layer is interdigitated with a second portion of said second electrode layer.
10. The capacitor as described in claim 9 further comprising:
at least one trench formed under said first electrode and said second electrode, and wherein said trench is filled with a conductive material.
11. The capacitor as described in claim 10 wherein said conductive material is in electrical contact with said first electrode.
12. The capacitor as described in claim 10 wherein said conductive material is polysilicon.
13. The capacitor as described in claim 9 further comprising:
a passivation layer formed over said first electrode and said second electrode wherein said passivation layer comprises a first opening over said first electrode and a second opening over said second electrode.
14. The capacitor as described in claim 13 further comprising:
a first metal ball formed in said first opening, wherein said first metal ball is electrically coupled to said first electrode; and
a second metal ball formed in said second opening, wherein said second metal ball is electrically coupled to said second electrode.
15. A method of fabricating a capacitor in a semiconductor substrate comprising a first surface and a second surface, said method comprising:
forming a first dielectric layer directly on a first portion of said first surface of said semiconductor substrate;
forming a first electrode layer directly over said first dielectric layer, wherein said first electrode layer is electrically insulated from said semiconductor substrate;
forming a second dielectric layer directly on a second portion of said first surface of said semiconductor substrate, wherein said first dielectric layer is separated from said second dielectric layer;
forming a second electrode layer directly over said second dielectric layer, wherein said first electrode, said second electrode, said first dielectric layer and said second dielectric layer form a plurality of capacitors in series, wherein a first portion of said first electrode layer is interdigitated with a second portion of said second electrode layer; and
forming a passivation layer above said first electrode and said second electrode.
16. The method as described in claim 15 further comprising:
forming a first opening in said passivation layer over said first electrode; and
forming a second opening in the passivation layer over said second electrode.
17. The method as described in claim 15 further comprising:
forming at least one trench under said first electrode and said second electrode, and wherein a portion of said first dielectric layer covers a sidewall of said at least one trench.
18. The method as described in claim 17 wherein said at least one trench is filled with a conductive material.