High mobility power metal-oxide semiconductor field-effect transistors
View Patent ↗High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.
1. A vertical trench silicon MOSFET comprising:
a (110) wafer including:
an orientation flat;
a trench perpendicular to the orientation flat of the (110) wafer, wherein the trench includes a plurality of trench surfaces; and
a channel, wherein the orientation flat is a [111] directed flat, and wherein the trench surfaces are bounded by {111} equivalent planes.
2. A channel structure for a vertical DMOSFET comprising:
a (110) wafer including:
an orientation flat;
a trench perpendicular to the orientation flat of the (110) wafer, wherein the trench includes a plurality of trench surfaces; and
a P channel, wherein the orientation flat is a [111] directed flat, and wherein the trench surfaces are bounded by {111} equivalent planes.
3. A p channel power MOSFET structure comprising:
a (110) wafer including:
an orientation flat;
a gate;
a source;
a trench perpendicular to the orientation flat of the (110) wafer, wherein the trench includes a plurality of trench surfaces; and
an inversion/accumulation channel, wherein the flat is a [111] directed flat, and wherein the trench surfaces are bounded by {111} equivalent planes.
4. A semiconductor comprising:
a (110) wafer including:
an orientation flat;
vertical DMOSFET means comprising:
a trench perpendicular to the orientation flat of the (110) wafer, wherein the trench includes a plurality of trench surfaces; and
P channel means, wherein the orientation flat is a [111] directed flat, and wherein the trench surfaces are bounded by {111} equivalent planes.
5. A p channel power MOSFET structure comprising:
a (110) wafer including:
an orientation flat;
gate means;
source means;
a trench perpendicular to the orientation flat of the (110) wafer, wherein the trench includes a plurality of trench surfaces; and
inversion/accumulation channel means, wherein the orientation flat is a [111] directed flat, and wherein the trench surfaces are bounded by {111} equivalent planes.