IP Library Granted Patent US 8,883,595
Granted Patent B2
US 8,883,595 · App. 11/710,041 · Granted Nov 11, 2014

Process for forming a short channel trench MOSFET and device formed thereby

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Quick Facts
Patent No.
US 8,883,595
App. No.
11/710,041
Granted
Nov 11, 2014
Kind
B2
Abstract

A process for forming a short channel trench MOSFET. The process includes forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant is adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant is n-type material.

Claims (24)

1. A process for forming a short channel trench MOSFET comprising:

forming a first implant at a bottom of a trench of said trench MOSFET wherein said trench comprises a space wherein a gate oxide is formed; and

forming a second implant that is tilted downward in its orientation moving in a direction with respect to said trench MOSFET from right to left to have an angle with respect to a horizontal plane and is implanted to remain confined to an area outside the right side of said space at a ninety degree angle from an outer side of said trench and from a vertical plane, wherein said second implant is adjusted so that it does not reach a bottom of said trench.

2. The process of claim 1 wherein said first implant is self-aligned to said trench bottom and defines said channel bottom.

3. The process of claim 1 wherein said second implant is an anti-pinching implant.

4. The process of claim 1 wherein said trench has a depth that determines a channel length of said trench MOSFET.

5. The process of claim 1 wherein said second implant is formed prior to the formation of contact and contact-clamping implants of said trench MOSFET.

6. The process of claim 1 wherein said second implant is formed at two twist angles.

7. The process of claim 1 wherein said first implant comprises an n-type dopant.

8. The process of claim 2 wherein said second implant comprises an n-type dopant.

9. The process of claim 8 wherein said second implant is performed through a contact window of said trench MOSFET.

10. A process of forming a short channel trench MOSFET comprising:

forming a substrate;

forming a trench in said substrate wherein said trench comprises a space wherein a gate oxide is formed;

forming a trench bottom implant at a bottom of said trench; and

forming a second implant that is tilted downward in orientation moving in a direction with respect to said trench MOSFET from right to left to have an angle with respect to a horizontal plane and is implanted to remain confined to an area outside the right side of said space at a ninety degree angle from an outer side of said trench and from a vertical plane, wherein said second implant does not reach said bottom of said trench.

11. The process of claim 10 wherein said trench bottom implant is self-aligned to said trench bottom and defines a channel bottom.

12. The process of claim 10 wherein said second implant is an anti-pinching implant.

13. The process of claim 10 wherein said trench has a depth that determines a channel length.

14. The process of claim 10 wherein said second implant is formed prior to the formation of contact and contact-clamping implants.

15. The process of claim 10 wherein said second implant is formed at two twist angles.

16. The process of claim 10 wherein said trench bottom implant comprises an n-type dopant.

17. The process of claim 11 wherein said second implant comprises an n-type dopant.

18. The process of claim 17 wherein said second implant is performed through a contact window of said trench MOSFET.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2007
From: LEE, ZACHARY
To: VISHAY-SILICONIX
Reel/Frame 019598/0447 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2007
From: LEE, ZACHARY; PATTANAYAK, DEVA
To: VISHAY-SILICONIX
Reel/Frame 018975/0066 →