IP Library Granted Patent US 9,947,770
Granted Patent B2
US 9,947,770 · App. 12/015,723 · Granted Apr 17, 2018

Self-aligned trench MOSFET and method of manufacture

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Quick Facts
Patent No.
US 9,947,770
App. No.
12/015,723
Granted
Apr 17, 2018
Kind
B2
Abstract

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

Claims (31)

1. A trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a drain region;

a plurality of gate regions disposed in a plurality of trenches above the drain region;

a plurality of gate insulator regions, wherein each of the plurality of gate insulator regions are disposed about a periphery of a respective one of the plurality of gate regions;

a plurality of field insulator regions, wherein each of the plurality of field insulator regions are disposed in a respective one of the plurality of trenches above a respective one of the plurality of gate regions;

a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, wherein the recessed mesas are aligned to the plurality of field insulator regions disposed in the plurality of trenches;

a plurality of body regions disposed in the recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region;

a plurality of body contact regions disposed in each body region adjacent the plurality of source regions;

a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, wherein the plurality of body contact regions are aligned to the plurality of source body contact spacers; and

a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the plurality of body contact regions to the plurality of source regions.

2. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1 , wherein the gate region is formed as a plurality of substantially parallel elongated structures.

3. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1 , wherein:

a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures; and

a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are substantially perpendicular to the first plurality of substantially parallel elongated structures.

4. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1 , wherein:

the drain region comprises an n-doped semiconductor;

the gate region comprises a n-doped semiconductor;

the gate insulator region comprises an oxide;

the plurality of source regions comprise a heavily n-doped semiconductor;

the body region comprises a p-doped semiconductor;

the plurality of body contact regions comprise a heavily p-doped semiconductor;

the plurality of source/body contact spacers comprise an oxide;

the source/body contact comprise a first metal; and

the plurality of source/body contact plugs comprise a second metal.

5. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1 , wherein:

the first metal comprises aluminum; and

the second metal comprises tungsten.

6. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1 , further comprising a drift region disposed between the drain region and the body region.

7. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 6 , wherein:

the drain region comprises a heavily n-doped semiconductor; and

the drift region comprises a lightly n-doped semiconductor.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2008
From: LI, JIAN; CHEN, KUO-IN; TERRIL, KYLE
To: VISHAY-SILICONIX
Reel/Frame 020377/0744 →