IP Library Granted Patent US 6,901,655
Granted Patent B2
US 6,901,655 · App. 10/797,866 · Granted Jun 7, 2005

Method for making overlay surface mount resistor

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Quick Facts
Patent No.
US 6,901,655
App. No.
10/797,866
Granted
Jun 7, 2005
Kind
B2
Abstract

A surface mount resistor includes an elongated piece of resistive material having strips of conductive material attached to its opposite ends. The strips of conductive material are separated to create an exposed central portion of the resistive material therebetween. According to the method the resistive strip is attached to a single co extensive strip of conductive material and a central portion of the conductive material is removed to create the exposed central portion of the resistive strip.

Claims (14)

1. A method for making a plurality of surface mount resistors comprising:

taking a resistive strip of electrically resistive material having an upper edge, a lower edge, a central portion between said upper and lower edges, a front flat surface and a rear flat surface;

taking a single conductive strip having an upper edge, a lower edge, a central portion between said upper edge and said lower edge, a front flat surface and a rear flat surface;

attaching said rear flat surface of said single conductive strip in complete covering relation over said front flat surface of said resistive strip;

modifying said overlying strip by removing said central portion of said single conductive strip to expose said central portion of said resistive strip whereby said modified overlying strip comprises an upper conductive strip and a lower conductive strip overlying spaced apart upper and lower portions of said front flat face of said resistive strip, respectively, said upper and lower conductive strips being separated from one another and being connected by said central portion of said resistance strip;

sectioning said overlying strip into a plurality of body members, each of said body members comprising an upper conductive section of said upper strip and a lower conductive section of said lower strip joined by a central resistive section of said exposed central portion of said resistance strip;

encapsulating said exposed central resistive section of each of said resistive strips with an electrically insulating material.

2. A method according to claim 1 and further comprising attaching a carrier strip to overlying strip, said sectioning step being done so as to leave said carrier strip interconnecting said plurality of body members.

3. A method according to claim 2 and further comprising removing said plurality of body members from said crier snip after said step of applying said encapsulating material.

4. A method according to claim 1 wherein said step of removing said central portion of said single conductive strip is done by a process selected from the group consisting essentially of grinding, milling or skiving.

5. A method of forming a surface mount resistor comprising:

taking a resistance strip, an upper conductive strip, and a lower conductive strip, each having an upper edge, a lower edge, a front flat surface and a rear surface;

attaching said rear surfaces of said upper and lower conductive strips to said front flat surface of said resistance strip in spaced parallel relationship to one another thereby leaving an exposed central portion of said resistance strip between and interconnecting said spaced apart upper and lower conductive strips;

applying an electrically insulating encapsulating material to said resistance strip so as to encapsulate said resistance strip within said encapsulating material between the upper and lower conductive strips, wherein the step of attaching said upper and lower conductive strips to said resistance strip comprises attaching a single conductive strip in complete covering relation over said flat front surface; of said resistive strip and removing a portion of said single conductive strip to create said spaced apart upper and lower conductive strips and to expose said central portion of said resistive strip.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE
Reel/Frame 049772/0898 →
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Dec 10, 2015
From: VISHAY DALE ELECTRONICS, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 037261/0616 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
RELEASE OF SECURITY INTEREST Recorded Dec 14, 2010
From: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
To: VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION; VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION; VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION; SILICONIX INCORPORATED, A DELAWARE CORPORATION; VISHAY MEASUREMENTS GROUP, INC., A DELAWARE CORPORATION; VISHAY GENERAL SEMICONDUCTOR, LLC, F/K/A GENERAL SEMICONDUCTOR, INC., A DELAWARE LIMITED LIABILITY COMPANY; VISHAY VITRAMON, INCORPORATED, A DELAWARE CORPORATION; YOSEMITE INVESTMENT, INC., AN INDIANA CORPORATION
Reel/Frame 025489/0184 →
SECURITY AGREEMENT Recorded Mar 2, 2010
From: VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC; VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY MEASUREMENTS GROUP, INC.
To: COMERICA BANK, AS AGENT
Reel/Frame 024006/0515 →