IP Library Granted Patent US 9,230,810
Granted Patent B2
US 9,230,810 · App. 12/873,147 · Granted Jan 5, 2016

System and method for substrate wafer back side and edge cross section seals

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Quick Facts
Patent No.
US 9,230,810
App. No.
12/873,147
Granted
Jan 5, 2016
Kind
B2
Abstract

Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Claims (13)

1. A method of growing epitaxial silicon on a silicon wafer, said method comprising:

depositing a layer of silicon oxide on all surfaces and edges of said silicon wafer;

removing said silicon oxide from a front surface of said silicon wafer;

depositing a layer of poly silicon only on a back surface of said silicon wafer, over said silicon oxide;

growing a layer of epitaxial silicon on said front surface of said silicon wafer;

growing another layer of epitaxial silicon on said layer of epitaxial silicon; and

doping a region of said layer of epitaxial silicon prior to said growing another layer of epitial silicon.

2. A method of growing epitaxial silicon on a silicon wafer, said method comprising:

depositing a layer of silicon oxide on all surfaces and edges of said silicon wafer;

removing said silicon oxide from a front surface of said silicon wafer;

depositing a layer of poly silicon on a back surface of said silicon wafer, over said silicon oxide;

growing a layer of epitaxial silicon on said front side of said silicon wafer; and

growing another layer of epitaxial silicon on said layer of epitaxial silicon, wherein said another layer of epitaxial silicon comprises a gap characterized by an absence of epitaxial silicon.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →