IP Library › Granted Patent US 7,394,150
Granted Patent B2
US 7,394,150 · App. 10/996,148 · Granted Jul 1, 2008

Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys

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Quick Facts
Patent No.
US 7,394,150
App. No.
10/996,148
Granted
Jul 1, 2008
Kind
B2
Abstract

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Claims (29)

1. A semiconductor package comprising:

a semiconductor die having a first terminal on a top surface of said die and at least a second terminal on a bottom surface of said die;

an upper lead frame in electrical contact with said first terminal, said upper lead frame having bent portions extending downward around a pair of opposite edges of said semiconductor die, each of said bent portions terminating in a foot;

a lower lead frame comprising at least two contacts, a first one of said contacts having a plurality of raised mesas formed in a top surface of said first contact, said mesas being separated by valleys;

a first solder layer connecting said first terminal of said die to said upper lead frame;

a second solder layer connecting said second terminal of said die to said first contact of said lower lead frame.

2. The semiconductor package of claim 1 wherein said second solder layer is thicker than said first solder layer.

3. The semiconductor package of claim 1 wherein a groove is formed in a lower surface of said upper lead frame.

4. The semiconductor package of claim 3 wherein said groove is formed in the shape of a cross on said lower surface of said upper lead frame.

5. The semiconductor package of claim 3 wherein said first solder layer extends into said groove.

6. The semiconductor package of claim 1 wherein said second solder layer covers a top surface of each of said mesas.

7. The semiconductor package of claim 1 comprising a third solder layer connecting said upper lead frame to a second one of said contacts of said lower lead frame.

8. The semiconductor package of claim 7 wherein said second one of said contacts has a cavity formed in a top surface thereof.

9. The semiconductor package of claim 1 comprising a protective capsule formed of a molding compound, said molding compounding separating said at least two contacts.

10. The semiconductor package of claim 9 wherein said valleys contain said molding compound.

11. The semiconductor package of claim 1 wherein a passivation layer overlies a portion of said die.

12. The semiconductor package of claim 1 wherein said upper lead frame comprises a pair of sidewalls that extend downward over a second pair of opposite edges of said die.

13. A package for a vertical MOSFET, said package comprising:

a semiconductor die containing said vertical MOSFET, said die having a drain terminal on a top surface of said die and a source terminal and a gate terminal on a bottom surface of said die;

an upper lead frame in electrical contact with said drain terminal, said upper lead frame having bent portions extending downward around opposite edges of said semiconductor die, each of said bent portions terminating in a foot;

a lower lead frame comprising a source contact, a gate contact, and a pair of drain contacts, each of said source contact and said gate contact having at least two raised mesas formed in a top surface thereof, said at least two raised mesas separated by a valley, said source, gate and drain contacts having coplanar bottom surfaces;

a first solder layer connecting said drain terminal to said upper lead frame;

a second solder layer connecting said source terminal to said source contact;

a third solder layer connecting said gate terminal to said gate contact; and

a protective capsule formed of a molding compound, portions of said molding compound separating said first and second contacts.

14. The package of claim 13 wherein said source contact comprises a plurality of paddle-like sections separated by slots, each of said paddle sections comprising a plurality of said raised mesas.

15. The semiconductor package of claim 6 wherein said second solder layer does not extend into said valleys.

16. The semiconductor package of claim 13 wherein said second solder layer covers a top surface of each of said at least two mesas.

17. The semiconductor package of claim 16 wherein said second solder layer does not extend into said valley.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.; VISHAY TECHNO COMPONENTS, LLC; VISHAY EFI, INC.; VISHAY VITRAMON, INC.; SPRAGUE ELECTRIC COMPANY
Reel/Frame 049826/0312 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Jan 21, 2011
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED; VISHAY SPRAGUE, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025675/0001 →
RELEASE OF SECURITY INTEREST Recorded Dec 14, 2010
From: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
To: VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION; VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION; VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION; SILICONIX INCORPORATED, A DELAWARE CORPORATION; VISHAY MEASUREMENTS GROUP, INC., A DELAWARE CORPORATION; VISHAY GENERAL SEMICONDUCTOR, LLC, F/K/A GENERAL SEMICONDUCTOR, INC., A DELAWARE LIMITED LIABILITY COMPANY; VISHAY VITRAMON, INCORPORATED, A DELAWARE CORPORATION; YOSEMITE INVESTMENT, INC., AN INDIANA CORPORATION
Reel/Frame 025489/0184 →
SECURITY AGREEMENT Recorded Mar 2, 2010
From: VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC; VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY MEASUREMENTS GROUP, INC.
To: COMERICA BANK, AS AGENT
Reel/Frame 024006/0515 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2005
From: KASEM, MOHAMMED; OWYANG, KING; KUO, FRANK; JAUNAY, SERGE ROBERT; MAO, SEN; OU, OSCAR; WANG, PETER; CHEN, CHANG-SHENG
To: SILICONIX INCORPORATED
Reel/Frame 016120/0930 →