Electrostatic discharge protection circuit for integrated circuits

1. An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) having integrated first and second electrostatic discharge protection components, comprising:

a first electrostatic discharge (ESD) protection component that has a multi-fingered structure; and a second electrostatic discharge (ESD) protection component coupled in series to said first electrostatic discharge (ESD) protection component that is approximately one half the size of said first electrostatic discharge (ESD) protection component,

wherein said first electrostatic discharge (ESD) protection component and said second electrostatic discharge (ESD) protection component are integrated and coupled via a buried layer to buried layer region wherein a first buried layer is formed underneath a p-well region of said first electrostatic discharge (ESD) protection component and a second buried layer region is formed underneath an n-sinker region of said second electrostatic discharge (ESD) protection component, and wherein a snapback holding voltage of said electrostatic discharge protection circuit is greater than an operating voltage of said electrostatic discharge protection circuit and a snapback condition is not sustained by said operating voltage and wherein a snapback trigger voltage of said electrostatic discharge protection circuit is lower than an oxide breakdown voltage of said IC and is different from said snapback holding voltage.

2. The ESD protection circuit of claim 1 wherein said first electrostatic discharge (ESD) protection component is a transistor.

3. The ESD protection circuit of claim 2 wherein said second electrostatic discharge (ESD) protection component is a Zener diode.

4. The ESD protection circuit of claim 3 wherein a portion of an operating voltage is sustained by said Zener diode when said Zener diode is conducting.

5. The ESD protection circuit of claim 3 wherein said Zener diode is integrated with said transistor.

6. The ESD protection circuit of claim 2 wherein said transistor is a MOSFET.

7. The ESD protection circuit of claim 3 wherein said transistor and said Zener diode are shut off after an ESD event.

8. An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) for providing protection during an ESD event, comprising:

a current flow control component that has a multi-fingered structure; and

a current flow direction control component coupled in series to said current flow control component that is approximately one half the size of said current flow control component, wherein said current flow control component and said current flow direction control component are integrated and coupled via a buried layer to buried layer region wherein a first buried layer is formed underneath a p-well region of said current flow control component and a second buried layer region is formed underneath an n-sinker region of said current flow direction control component, and

wherein a snapback holding voltage of said electrostatic discharge protection circuit is greater than an operating voltage of said electrostatic discharge protection circuit and a snapback condition is not sustained by said operating voltage and wherein a snapback trigger voltage of said electrostatic discharge protection circuit lower than an oxide breakdown voltage of said IC and is different from said snapback holding voltage.

9. The ESD protection circuit of claim 8 wherein said current flow control component is a transistor.

10. The ESD protection circuit of claim 9 wherein said current flow direction control component is a Zener diode.

11. The ESD protection circuit of claim 10 powered by an operating voltage wherein a portion of said operating voltage is sustained by said Zener diode when said Zener diode is conducting.

12. The ESD protection circuit of claim 11 wherein said Zener diode is integrated with said transistor.

13. The ESD protection circuit of claim 9 wherein said transistor is a MOSFET.

14. The ESD protection circuit of claim 10 wherein said transistor and said Zener diode are shut off after an ESD event.

15. An integrated circuit (IC) with electrostatic discharge (ESD) protection, comprising:

an input;

an integrated circuit die coupled to said input;

a first electrostatic discharge (ESD) protection component coupled to said input that has a multi-fingered structure; and

a second electrostatic discharge (ESD) protection component coupled in series to said first electrostatic discharge (ESD) protection component that is approximately one half the size of said first electrostatic discharge (ESD) protection component, wherein said first electrostatic discharge (ESD) protection component and said second electrostatic discharge (ESD) protection component are integrated and coupled via a buried layer to buried layer region wherein a first buried layer is formed underneath a p-well region of said first electrostatic discharge (ESD) protection component and a second buried layer region is formed underneath an n-sinker region of said second electrostatic discharge (ESD) protection component, and

wherein a snapback holding voltage of said electrostatic discharge protection circuit is greater than an operating voltage of said electrostatic discharge protection circuit and a snapback condition is not sustained by said operating voltage and wherein a snapback trigger voltage of said electrostatic discharge protection circuit is lower than an oxide breakdown voltage of said IC and is different from said snapback holding voltage.

16. The integrated circuit of claim 15 wherein said first electrostatic discharge (ESD) protection component is a transistor.

17. The integrated circuit of claim 16 wherein said second electrostatic discharge (ESD) protection component is a Zener diode.

18. The integrated circuit of claim 17 powered by an operating voltage wherein a portion of said operating voltage is sustained by said Zener diode when said Zener diode is conducting.

19. The integrated circuit of claim 17 wherein said Zener diode is integrated with said transistor.

20. The integrated circuit of claim 15 wherein said transistor is a MOSFET.

21. The integrated circuit of claim 17 wherein after said ESD event is ended said transistor and said Zener diode are shut off.