IP Library Granted Patent US 9,423,812
Granted Patent B2
US 9,423,812 · App. 13/551,516 · Granted Aug 23, 2016

Current mode boost converter using slope compensation

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Quick Facts
Patent No.
US 9,423,812
App. No.
13/551,516
Granted
Aug 23, 2016
Kind
B2
Abstract

A boost converter circuit that includes a power supply, an inductor coupled to the power supply to receive current from the power supply, a diode coupled to receive current from the inductor and coupled to provide current to a load as an output, an inductor switch coupled to a node between the inductor and the diode for selectively switching current from the inductor anyway from the diode, and a ramp circuit. The ramp circuit is coupled to the node between the inductor and the diode, and is configured to selectively sample a voltage at the node between the inductor and the diode via a sampling switch and use the sampled signal to produce a stabilization ramp to stabilize the output.

Claims (39)

1. A boost converter circuit, comprising:

a power supply;

an inductor coupled to the power supply to receive current from the power supply;

a diode coupled to receive current from the inductor and coupled to provide current to a load as an output;

an inductor switch coupled to a node between the inductor and the diode for selectively switching an inductor current to receive a current to the inductor from the power supply, or output the inductor current to a load; and

a ramp circuit coupled to the node between the inductor and the diode, wherein the ramp circuit is configured to selectively sample a voltage at the node between the inductor and the diode via a sampling switch and use the sampled signal to produce a stabilization ramp to stabilize the output.

2. The boost converter circuit of claim 1 , wherein the boost converter circuit is packaged as an integrated circuit device.

3. The boost converter circuit of claim 2 , wherein the integrated circuit device does not provide a pin for the output voltage.

4. The boost converter circuit of claim 1 , wherein the stabilization ramp is configured to insure stability for duty cycle ratios greater than 0.5.

5. The boost converter circuit of claim 1 , wherein the stabilization ramp depends on the output voltage level and is added to increase a receiving current ramp of the inductor by adding the stabilization ramp.

6. The boost converter circuit of claim 1 , wherein the ramp circuit is configured to selectively sample the voltage at the node between the inductor and the diode at a time when the inductor switch is off and the voltage is stabilized.

7. The boost converter circuit of claim 6 , wherein the voltage at the node is substantially similar to the output voltage level.

8. The boost converter circuit of claim 1 , wherein the ramp circuit comprises:

the sampling switch; and

a sampling capacitor coupled to the sampling switch to receive and store the voltage at the node between the inductor and the diode.

9. A boost converter integrated circuit device, comprising:

a power supply input for receiving a power supply;

an inductor coupled to the power supply input to receive current from the power supply;

a diode coupled to receive current from the inductor and coupled to provide current to a load coupled to the integrated circuit device as an output;

an inductor switch coupled to a node between the inductor and the diode for selectively switching an inductor current to receive a current to the inductor from the power supply, or to output the inductor current to the load; and

a ramp circuit coupled to the node between the inductor and the diode, wherein the ramp circuit is configured to selectively sample a voltage at the node between the inductor and the diode via a sampling switch and use the sampled signal to produce a stabilization ramp to stabilize the output.

10. The boost converter integrated circuit device of claim 9 , wherein the integrated circuit device does not provide a pin for the output voltage.

11. The boost converter integrated circuit device of claim 9 , wherein the stabilization ramp is configured to insure stability for duty cycle ratios greater than 0.5.

12. The boost converter integrated circuit device of claim 9 , wherein the stabilization ramp depends on the output voltage level and is based on increasing a receiving current ramp of the inductor by adding the stabilization ramp.

13. The boost converter integrated circuit device of claim 9 , wherein the voltage at the node between the inductor and the diode is sampled at a time when the inductor switch is off and the voltage is stabilized.

14. The boost converter integrated circuit device of claim 9 , wherein the ramp circuit comprises:

the sampling switch; and

a sampling capacitor coupled to the sampling switch to receive and store the voltage at the node between the inductor and the diode.

15. A method comprising:

receiving a current from a power supply at an inductor coupled to the power supply;

receiving current from the inductor at a diode coupled to the inductor;

outputting current from the diode to a load coupled to the diode as an output voltage;

selectively switching an inductor current to either receive a current to the inductor from the power supply, or output the inductor current to the load, by an inductor switch coupled to a node between the inductor and the diode; and

selectively sampling a voltage at the node between the inductor and the diode via a sampling switch of a ramp circuit coupled to the node via the sampling switch, wherein the ramp circuit is configured to use the sampled signal to produce a stabilization ramp to stabilize the output voltage, a boost converter circuit comprising the inductor, the diode, the inductor switch, and the ramp circuit.

16. The method of claim 15 , wherein the boost converter circuit is packaged as an integrated circuit device.

17. The method of claim 16 , wherein the integrated circuit device does not provide a pin for the output voltage.

18. The method of claim 15 , wherein the stabilization ramp is configured to insure stability for duty cycle ratios greater than 0.5.

19. The method of claim 15 , wherein the stabilization ramp is based on increasing a receiving current ramp of the inductor by the stabilizing ramp, which depends on the output voltage level.

20. The method of claim 15 , wherein the ramp circuit is configured to selectively sample the voltage at the node between the inductor and the diode at a time when the inductor switch is off and the voltage is stabilized.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2019
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: VISHAY DALE ELECTRONICS, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED
Reel/Frame 049785/0771 →
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
SECURITY AGREEMENT Recorded Sep 5, 2013
From: VISHAY INTERTECHNOLOGY, INC.; VISHAY DALE ELECTRONICS, INC.; SILICONIX INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 031170/0001 →