IP Library Granted Patent US 9,331,142
Granted Patent B2
US 9,331,142 · App. 14/819,826 · Granted May 3, 2016

Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,331,142
App. No.
14/819,826
Granted
May 3, 2016
Kind
B2
Abstract

A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.

Claims (12)

1. A method of fabricating a semiconductor device, comprising:

forming a first oxide layer over a portion of a semiconductor substrate formed from a first semiconductor material having a first conductivity type such that a remaining portion of the semiconductor substrate is exposed;

forming a protective layer on a first surface of the semiconductor substrate and the first oxide layer;

introducing a dopant of the second conductivity type into the semiconductor substrate through the protective layer to form a junction layer that defines a junction with the semiconductor substrate;

forming a first conductive layer over the junction layer; and

forming a second conductive layer on a second surface of the semiconductor substrate opposing the first surface of the semiconductor substrate.

2. The method of claim 1 wherein the protective layer comprises a conductive material.

3. The method of claim 2 wherein the protective layer comprises polysilicon.

4. The method of claim 1 further comprising removing the protective layer after introducing the dopant of the second conductivity type.

5. The method of claim 4 wherein the protective layer comprises a non-conductive material.

6. The method of claim 1 further comprising diffusing the dopant implanted in the semiconductor substrate at an elevated temperature.

7. The method of claim 1 wherein the dopant is introduced into the semiconductor substrate by ion implantation.

Assignments (1)
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →