IP Library Granted Patent US 9,787,309
Granted Patent B2
US 9,787,309 · App. 14/486,926 · Granted Oct 10, 2017

Methods for preventing reverse conduction

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Quick Facts
Patent No.
US 9,787,309
App. No.
14/486,926
Granted
Oct 10, 2017
Kind
B2
Abstract

In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground.

Claims (32)

1. A method comprising:

detecting a defined voltage difference between an output and a voltage supply of an integrated circuit; and

after said detecting, preventing said integrated circuit from turning on using a switching element that couples an enable input of said integrated circuit to ground, a resistance comprising first and second terminals, said first terminal being coupled to a control terminal of said switching element and said second terminal being coupled to said ground.

2. The method of claim 1 , wherein said switching element comprises a transistor.

3. The method of claim 1 , wherein said detecting is performed by another switching element coupled to said output and said voltage supply.

4. The method of claim 3 , further comprising:

detecting a voltage at both said voltage supply and said enable input.

5. The method of claim 4 , further comprising:

after said detecting said voltage at both, allowing said integrated circuit to operate free of interference by said switching element.

6. The method of claim 1 , wherein said switching element comprises a body that is coupled to said ground.

7. The method of claim 6 , wherein said detecting is performed by another switching element coupled to said output and said voltage supply.

8. The method of claim 1 , wherein said preventing comprises preventing a load switch of said integrated circuit from turning on.

9. A method comprising:

detecting a defined voltage difference between an output pin and a voltage supply pin of an integrated circuit; and

after said detecting, preventing said integrated circuit from turning on using a switching element that couples an enable pin of said integrated circuit to ground, a resistance comprising first and second terminals, said first terminal being coupled to a control terminal of said switching element and said second terminal being coupled to said ground.

10. The method of claim 9 , wherein said switching element comprises a transistor.

11. The method of claim 9 , wherein said detecting is performed by another switching element coupled to said output pin and said voltage supply pin.

12. The method of claim 11 , further comprising:

detecting a voltage at both said voltage supply pin and said enable pin.

13. The method of claim 12 , further comprising:

after said detecting said voltage at both, allowing said integrated circuit to operate free of interference by said switching element.

14. The method of claim 9 , wherein said preventing comprises preventing a load switch of said integrated circuit from turning on.

15. A method comprising:

detecting a defined voltage difference between an output and a voltage supply of a semiconductor chip; and

after said detecting, preventing said semiconductor chip from turning on using a switching element that couples an enable input of said semiconductor chip to ground, a resistance comprising first and second terminals, said first terminal being coupled to a control terminal of said switching element and said second terminal being coupled to said ground.

16. The method of claim 15 , wherein said switching element comprises a transistor.

17. The method of claim 16 , wherein said detecting is performed by another transistor coupled to said output and said voltage supply.

18. The method of claim 15 , further comprising:

detecting a voltage at both said voltage supply and said enable input of said semiconductor chip.

19. The method of claim 18 , further comprising:

after said detecting said voltage at both, allowing said semiconductor chip to operate free of interference by said switching element.

20. The method of claim 15 , wherein said preventing comprises preventing a load switch of said semiconductor chip from turning on.

Assignments (1)
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
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