Edge termination for super junction MOSFET devices
View Patent ↗In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N− type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.
1. A Super Junction metal oxide semiconductor field effect transistor (MOSFET) device comprising:
a substrate;
a charge compensation region located above said substrate and comprising a plurality of columns of P type dopant within an N type dopant region;
an N− type dopant layer located above said charge compensation region;
a source, a portion of said source is located above said N− type dopant layer;
a drain, a portion of said drain is located above said N− type dopant layer; and
an edge termination structure located between said source and said drain, a portion of said edge termination structure is located above said N− type dopant layer;
said plurality of columns of P type dopant are similar in height beneath said source, said edge termination structure, and said drain.
2. The Super Junction MOSFET device of claim 1 , wherein said edge termination structure comprises a field ring.
3. The Super Junction MOSFET device of claim 2 , wherein said field ring is free of physically contacting any of said plurality of columns of P type dopant.
4. The Super Junction MOSFET device of claim 1 , further comprising a plurality of edge termination structures.
5. The Super Junction MOSFET device of claim 4 ,
wherein said plurality of edge termination structures comprises a plurality of field rings.
6. The Super Junction MOSFET device of claim 4 , wherein said plurality of edge termination structures comprises a plurality of field plates.
7. The Super Junction MOSFET device of claim 1 , wherein said edge termination structure comprises a field plate.
8. A Super Junction metal oxide semiconductor field effect transistor (MOSFET) device comprising:
a substrate;
a charge compensation region located above said substrate and comprising a plurality of columns of N type dopant within a P type dopant region;
a P− type dopant layer located above said charge compensation region;
a source, a portion of said source is located above said P− type dopant layer;
a drain, a portion of said drain is located above said P− type dopant layer; and
an edge termination structure located between said source and said drain, a portion of said edge termination structure is located above said P− type dopant layer;
said plurality of columns of N type dopant are similar in height beneath said source, said edge termination structure, and said drain.
9. The Super Junction MOSFET device of claim 8 , wherein said edge termination structure comprises a field ring.
10. The Super Junction MOSFET device of claim 9 , wherein said field ring is free of physically contacting any of said plurality of columns of N type dopant.
11. The Super Junction MOSFET device of claim 8 , further comprising a plurality of edge termination structures.
12. The Super Junction MOSFET device of claim 11 ,
wherein said plurality of edge termination structures comprises a plurality of field rings.
13. The Super Junction MOSFET device of claim 11 , wherein said plurality of edge termination structures comprises a plurality of field plates.
14. The Super Junction MOSFET device of claim 8 , wherein said edge termination structure comprises a field plate.
15. A method comprising:
generating a charge compensation region of a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device, wherein said charge compensation region is located above a substrate and comprising a plurality of columns of first type dopant within a second type dopant region, said Super Junction MOSFET device comprises a source and a drain;
generating a layer located above said charge compensation region and comprising a second type dopant having a lower concentration than said second type dopant region, a portion of said source is located above said layer, a portion of said drain is located above said layer; and
generating an edge termination structure located between said source and said drain, a portion of said edge termination structure is located above said layer;
said plurality of columns of first type dopant are similar in height beneath said source, said edge termination structure, and said drain.
16. The method of claim 15 , wherein said first type dopant comprises a P type dopant and said second type dopant comprises an N type dopant.
17. The method of claim 15 , wherein said first type dopant comprises an N type dopant and said second type dopant comprises a P type dopant.
18. The method of claim 15 , wherein said edge termination structure comprises a field ring.
19. The method of claim 15 ,
wherein said edge termination structure comprises a field plate.
20. The method of claim 15 , wherein said generating said edge termination structure further comprising generating a plurality of edge termination structures.