Semiconductor device having reduced gate charges and superior figure of merit

1. A semiconductor device comprising:

a planar first epitaxial layer; and

a plurality of trench-like structures that extend into a second epitaxial layer coupled to the first epitaxial layer, said plurality of trench-like structures comprising:

a first plurality of said plurality of trench-like structures, said first plurality comprising first trench-like structures, each trench-like structure in said first plurality comprising a gate electrode contacted to gate metal and insulated from source metal by an intervening oxide layer, each trench-like structure in said first plurality further comprising a source electrode of polysilicon material contacted to said source metal, wherein said gate electrode is separated from said second epitaxial layer by a gate oxide, and wherein said source electrode is separated from said second epitaxial layer by a shield oxide; and

a second plurality of said plurality of trench-like structures, said second plurality comprising second trench-like structures, said second trench-like structures interleaved with said first trench-like structures in alternating fashion such that every other of said plurality of trench-like structures is one of said second trench-like structures, wherein each of said second trench-like structures is adjacent to both a respective first source region and a respective second source region, wherein each trench-like structure of said second trench-like structures is filled with said polysilicon material to form only one polysilicon region within said each trench-like structure of said second trench-like structures, wherein each said only one polysilicon region is electrically and physically contacted to said source metal via a source contact and is separated from said second epitaxial layer by said shield oxide, wherein each said only one polysilicon region is also electrically and physically contacted to said gate metal via a gate contact, and wherein a bottom surface of said only one polysilicon region and a bottom surface of said source electrode are aligned with each other substantially in a same plane that is parallel to said planar first epitaxial layer.

2. The semiconductor device of claim 1 wherein each said polysilicon region is contacted to said source metal at a respective top surface of each said only one polysilicon region, and wherein each said top surface coincides with a top surface of said gate electrode.

3. The semiconductor device of claim 1 comprising a layer of said source metal that traverses said first plurality of said plurality of trench-like structures and said second plurality of said plurality of trench-like structures, wherein said source electrode is contacted to said source metal outside an active core region of said semiconductor device and wherein said source electrode is insulated from said layer of said source metal inside said active core region, and wherein said second trench-like structures are contacted to said layer of said source metal inside said active core region.

4. The semiconductor device of claim 1 wherein said source metal traverses said first plurality of said plurality of trench-like structures and said second plurality of said plurality of trench-like structures, wherein said gate electrode is situated between said source electrode and said source metal.

5. The semiconductor device of claim 1 comprising a high side metal-oxide-semiconductor field-effect transistor (MOSFET) in a direct current (DC)-to-DC converter.

6. The semiconductor device of claim 1 wherein each said only one polysilicon region within said each trench-like structure of said second trench-like structures is also contacted to said gate metal.

7. The semiconductor device of claim 1 wherein each trench-like structure in said plurality of trench-like structures is adjacent to both a respective first source region and a respective second source region.

8. The semiconductor device of claim 1 wherein said first plurality of said plurality of trench-like structures and said second plurality of said plurality of trench-like structures extend to a same depth in said second epitaxial layer.

9. The semiconductor device of claim 1 wherein said plurality of trench-like structures are in an active core region of said semiconductor device, wherein one-half of said plurality of trench-like structures in said active core region comprise said first plurality of said plurality of trench-like structures and wherein one-half of said plurality of trench-like structures in said active core region comprise said second plurality of said plurality of trench-like structures.

10. The semiconductor device of claim 1 wherein a top surface of said only one polysilicon region and a top surface of said gate electrode are aligned with each other in a same plane that is parallel to said planar first epitaxial layer.

11. A semiconductor device comprising:

a planar first epitaxial layer; and

a plurality of trench-like structures that extend into a second epitaxial layer, said plurality of trench-like structures comprising:

a first plurality of split-gate first structures, each of said split-gate first structures comprising a first electrode region of polysilicon material and also comprising a second electrode region of said polysilicon material, said first plurality of said plurality of trench-like structures including a split-gate first trench-like structure, wherein said second electrode is separated from said second epitaxial layer by a gate oxide, and wherein said first electrode is separated from said second epitaxial layer by a shield oxide; and

a second plurality of second structures, each second structure of said second structures comprising only one polysilicon region of said polysilicon material that fills said each second structure, wherein each said only one polysilicon region is electrically and physically in contact with source metal via a source contact and is separated from said second epitaxial layer by said shield oxide, wherein each said only one polysilicon region is also electrically and physically contacted to gate metal via a gate contact, and wherein a bottom surface of said only one polysilicon region and a bottom surface of said first electrode region are aligned with each other substantially in a same plane that is parallel to said planar first epitaxial layer, said first plurality of split-gate first structures comprising half of said plurality of trench-like structures and said second plurality of second structures comprising the remainder of said plurality of trench-like structures, said second plurality of second structures interleaved with said first plurality of split-gate first structures in alternating fashion such that every other of said trench-like structures in said plurality of trench-like structures is one of said second trench-like structures, said second plurality of second structures including a second trench-like structure, wherein a first source region and a second source region are between said split-gate first trench-like structure and said second trench-like structure, said first source region adjacent to said split-gate first trench-like structure and said second source region adjacent to said second-like structure trench; and

a layer comprising said source metal that is insulated from said first split gate structures within an active region of said semiconductor device and is in contact with each polysilicon region of said plurality of disabled second structures within said active region.

12. The semiconductor device of claim 11 wherein each said first electrode region comprises a source electrode contacted to said source metal outside said active region, and wherein each said second electrode comprises a gate electrode contacted to said gate metal outside said active region.

13. The semiconductor device of claim 12 wherein each said gate electrode is situated between a respective source electrode and said layer comprising said source metal, and wherein said gate electrode is insulated from said layer comprising said source metal and also from said respective source electrode.

14. The semiconductor device of claim 11 wherein each said polysilicon region is contacted to said source metal at a respective top surface of each said only one polysilicon region, and wherein each said top surface is coplanar with a top surface of each said first electrode region.

15. The semiconductor device of claim 12 wherein each said only one polysilicon region that fills said each disabled second structure is also in contact with said gate metal.

16. The semiconductor device of claim 11 wherein a top surface of said only one polysilicon region and a top surface of said second electrode region are aligned with each other in a same plane that is parallel to said planar first epitaxial layer.