IP Library Granted Patent US 10,903,163
Granted Patent B2
US 10,903,163 · App. 15/263,882 · Granted Jan 26, 2021

Trench MOSFET with self-aligned body contact with spacer

Inventors: Lingpeng Guan (San Jose, CA); Kyle Terrill (Santa Clara, CA); Seokjin Jo (Santa Clara, CA)
Assignee: Vishay-Siliconix, LLC
H01L23/5283H01L29/0869H01L29/1095H01L29/41766H01L29/456H01L29/66719H01L29/66727H01L29/66734H01L29/7813H01L29/407
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Quick Facts
Patent No.
US 10,903,163
App. No.
15/263,882
Granted
Jan 26, 2021
Kind
B2
Abstract

Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate. Each of the trenches comprises a gate electrode. The semiconductor device also includes a body contact trench formed in the semiconductor substrate between the gate trenches. The body contact trench has a lower width at the bottom of the body contact trench and an ohmic body contact implant beneath the body contact trench. The horizontal extent of the ohmic body contact implant is not greater than the lower width of the body contact trench.

Claims (37)

1. A semiconductor device comprising:

a semiconductor substrate;

at least two gate trenches formed in said semiconductor substrate, wherein each of said trenches comprises a gate electrode;

a body contact trench formed in said semiconductor substrate between said gate trenches, having a lower width at the bottom of said body contact trench,

wherein said body contact trench extends to a depth greater than a maximum depth of a source region; and

an ohmic body contact implant beneath said body contact trench, wherein a horizontal extent of an entirety of said ohmic body contact implant is less than said lower width of said body contact trench.

2. The semiconductor device of claim 1 further comprising a plurality of spacers on the sides of said body contact trench.

3. The semiconductor device of claim 2 wherein said spacers are characterized as having a thickness in the range of 0.03 to 0.06 μm.

4. The semiconductor device of claim 3 wherein a horizontal extent of said ohmic body contact implant differs from said lower width of said body contact trench by about said thickness of said spacers from each side.

5. The semiconductor device of claim 2 wherein said spacers comprise nitride.

6. The semiconductor device of claim 2 wherein said spacers comprise chemical vapor deposition (CVD) oxide.

7. The semiconductor device of claim 1 further comprising a shield electrode, disposed below and electrically isolated from said gate electrode, in at least one of said gate trenches.

8. A semiconductor device comprising:

a semiconductor substrate;

at least two gate trenches formed in said semiconductor substrate, wherein each of said trenches comprises a gate electrode;

a body contact trench formed in said semiconductor substrate between said gate trenches, said body contact trench characterized as having a substantially constant sidewall slope to a first depth;

a body contact trench extension formed in said semiconductor substrate extending from the bottom of said body contact trench, wherein a sidewall of said body contact trench extension is disjoint with said sidewall slope of said body contact trench; and

an ohmic body contact implant beneath said body contact trench extension, wherein a horizontal extent of all of said ohmic body contact implant is not greater than a width of said body contact trench at said first depth.

9. The semiconductor device of claim 8 further comprising a plurality of spacers on the sides of said body contact trench.

10. The semiconductor device of claim 9 wherein an sidewall of said body contact trench extension is offset from a corresponding sidewall of said body contact trench by a thickness of said spacer.

11. The semiconductor device of claim 8 wherein a slope of sidewalls of said body contact trench extension is different that said slope of said body contact trench.

12. The semiconductor device of claim 8 wherein a slope of sidewalls of said body contact trench extension is substantially vertical.

13. The semiconductor device of claim 8 wherein body contact trench extension extends about 0.1 to 0.3 μm below said first depth.

14. The semiconductor device of claim 8 further comprising a shield electrode, disposed below and electrically isolated from said gate electrode, in at least one of said gate trenches.

15. A semiconductor device comprising:

a semiconductor substrate;

at least two gate trenches formed in said semiconductor substrate, wherein each of said trenches comprises a gate electrode;

a body contact trench formed in said semiconductor substrate between said gate trenches;

an ohmic body contact implant beneath said body contact trench, wherein said ohmic body contact implant is entirely beneath said body contact trench, and

wherein said ohmic body contact implant is formed at a depth greater than a maximum depth of a source region,

wherein a maximum horizontal extent of said ohmic body contact implant is less than a horizontal extent of the lowest portion of said body contact trench.

16. The semiconductor device of claim 15 further comprising a plurality of spacers on the sides of said body contact trench.

17. The semiconductor device of claim 16 wherein said spacers are characterized as having a thickness in the range of 0.03 to 0.06 μm.

18. The semiconductor device of claim 15 further comprising a shield electrode, disposed below and electrically isolated from said gate electrode, in at least one of said gate trenches.

19. The semiconductor device of claim 15 wherein a depth of said body contact trench is less than 0.5 μm.

20. The semiconductor device of claim 9 wherein said spacers are characterized as having a thickness in the range of 0.03 to 0.06 μm.

21. The semiconductor device of claim 8 wherein sidewalls of said body contact trench extension are more vertical than said sidewalls of said body contact trench.

Assignments (3)
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
EMPLOYEE AGREEMENT Recorded Oct 31, 2016
From: GUAN, LINGPENG
To: VISHAY-SILICONIX
Reel/Frame 040522/0707 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2016
From: TERRILL, KYLE; JO, SEOKJIN
To: VISHAY-SILICONIX
Reel/Frame 039719/0118 →
Continuity (2)
Provisional Application 62243502 · Oct 19, 2015
Related Publication 20170110404A1 · Apr 20, 2017