IP Library Granted Patent US 10,224,426
Granted Patent B2
US 10,224,426 · App. 15/643,306 · Granted Mar 5, 2019

High-electron-mobility transistor devices

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Quick Facts
Patent No.
US 10,224,426
App. No.
15/643,306
Granted
Mar 5, 2019
Kind
B2
Abstract

A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.

Claims (41)

1. A device, comprising:

a first high electronic mobility transistor (HEMT) comprising:

a first gate;

a source coupled to the first gate; and

a drain coupled to the first gate; and

a second HEMT comprising:

a second gate coupled to the source and to the drain;

wherein the first gate comprises a first contact and a first region having a first concentration of a dopant, wherein the second gate comprises a second contact and a second region having a second concentration of the dopant, and wherein the second concentration is less than the first concentration.

2. The device of claim 1 , further comprising a metal connection that connects the second gate to the source.

3. The device of claim 1 , wherein the dopant comprises a p-type dopant.

4. An electronic device, comprising:

a first field effect transistor (FET) comprising:

a layer comprising gallium; and

a first gate; and

a second FET comprising:

the layer comprising gallium; and

a second gate;

a first region disposed between the first gate and the layer comprising gallium, wherein the first region comprises a first dose of an implant material; and

a second region disposed between the second gate and the layer comprising gallium, wherein the second region comprises a second dose of the implant material and wherein the second dose is less than the first dose;

wherein the first FET and the second FET are coupled to a same source and to a same drain.

5. The electronic device of claim 4 , wherein the layer comprising gallium comprises aluminum gallium nitride (AlGaN), and wherein the electronic device further comprises:

a source region formed in the layer comprising AlGaN;

a drain region formed in the layer comprising AlGaN;

a two-dimensional electron gas (2DEG) layer coupled to the layer comprising AlGaN;

a second layer comprising GaN coupled to the layer comprising AlGaN;

a buffer layer coupled to the second layer; and

a substrate comprising silicon coupled to the buffer layer.

6. The electronic device of claim 4 , wherein the implant material comprises fluorine.

7. An electronic device, comprising:

a first field effect transistor (FET) comprising:

a source;

a drain; and

a first configuration for a structure comprising a first gate and a layer comprising gallium, the first configuration coupled to the source and to the drain; and

a second FET comprising:

a second configuration for a structure comprising a second gate and the layer comprising gallium, the second configuration coupled to the source and to the drain, wherein the second configuration is different from the first configuration;

wherein the first configuration comprises a first region disposed between the first gate and the layer comprising gallium, wherein the first region comprises a first thickness of an insulating material, wherein the second configuration comprises a second region disposed between the second gate and the layer comprising gallium, wherein the second region comprises a second thickness of an insulating material, and wherein the second thickness is less than the first thickness.

8. The electronic device of claim 7 , wherein the layer comprising gallium comprises aluminum gallium nitride (AlGaN), wherein the source and the drain are in the layer comprising AlGaN, and wherein the electronic device further comprises:

a two-dimensional electron gas (2DEG) layer coupled to the layer comprising AlGaN;

a second layer comprising GaN coupled to the 2DEG layer;

a buffer layer coupled to the second layer; and

a substrate comprising silicon coupled to the buffer layer.

Assignments (2)
SECURITY INTEREST Recorded Jun 12, 2019
From: VISHAY DALE ELECTRONICS, INC.; DALE ELECTRONICS, INC.; VISHAY DALE ELECTRONICS, LLC; VISHAY-DALE, INC.; VISHAY INTERTECHNOLOGY, INC.; SILICONIX INCORPORATED; VISHAY-SILICONIX, INC.; VISHAY-SILICONIX; VISHAY SPRAGUE, INC.; VISHAY EFI, INC.; SPRAGUE ELECTRIC COMPANY; VISHAY GENERAL SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 049440/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2017
From: SHIBIB, AYMAN; TERRILL, KYLE
To: VISHAY-SILICONIX
Reel/Frame 042926/0943 →