Emulated atomic instruction sequences in a multiprocessor system
View Patent ↗A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and performing by the emulator the atomic instruction for the processor using the data and the address location from the request.
1. A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, the method comprising the steps of:
(a) providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction;
(b) receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location, wherein the first processor does not support the atomic instruction; and
(c) performing by the emulator the atomic instruction for the first processor using the data and the address location from the request.
2. The method of claim 1 wherein step (a) further includes the step of: assigning a respective register set to each processor requiring service from the atomic instruction emulator.
3. The method of claim 2 wherein step (a) further includes the step of providing the emulator with a number of register set is equal to the number of processors available on the bus.
4. The method of claim 1 wherein each register set includes an address register for holding an address pointer, a result register far storing data read from the specified address, and a data register for storing the data to be written to the address.
5. The method of claim 4 wherein the request comprises separate commands specifying operations to be performed on the register set assigned to the processor.
6. The method of claim 5 wherein the request includes a write command to write data to the data register, a write address command to write an address pointer to the address register, and a read command to read the results register.
7. The method of claim 5 wherein step (b) further includes the step of queuing requests received from multiple processors.
8. The method of claim 5 wherein step (b) further includes the step of: processing the request by storing the data from the write data command to the data register and storing the address pointer from the write address command to the address register.
9. The method of claim 1 wherein step (c) further includes the step of: requesting the bus with a lock and setting an internal busy signal.
10. The method of claim 9 further including the step of: splitting any master that attempts to read the contents of the result register while the emulator is in the busy state.
11. The method of claim 9 further including the step of: if the lock is granted, using a state machine to generate an atomic instruction sequence for the processor.
12. The method of claim 11 further including the step of: performing a write instruction to write the value in the data register to an address location referred to by the address pointer register.
13. The method of claim 12 further including the step of: a read instruction to read the value in the result register.
14. The method of claim 12 further including the step of: clearing the busy state and any split masters after the write cycle is complete.
15. The method of claim 12 further including the step of: performing a modify command between the read and write instructions to perform counting operations on the data written to the shared resource.
16. The method of claim 1 further including the step of: notifying the processor that the atomic instruction sequence has completed using an interrupt controller.
17. An atomic instruction emulator, comprising:
a slave control for receiving a request to perform an atomic instruction on a shared resource on a bus that supports an atomic instruction from at least one processor coupled to the bus that does not support the atomic instruction;
at least one register set for implementing an atomic instruction sequence by storing data and an address within the shared resource specified in the request;
a state machine for performing an atomic instruction pair on the behalf of the non-complying processor by
obtaining a bus lock,
reading a value from the address of the shared resource pointed to by the address stored in the register set and saving the value in a register within the register set,
writing the data stored in the register set to the address of the shared,
and reading the value saved in the register in the register set; and a master control for returning the value to the requesting processor.
18. The atomic instruction emulator of claim 17 further including a queue for queuing requests received over the bus.
19. The atomic instruction emulator of claim 18 wherein a respective register set is assigned to each processor on the bus requiring emulation service.
20. The atomic instruction emulator of claim 19 wherein the emulator includes a number of register sets equal to the number of processors available on the bus.
21. The atomic instruction emulator of claim 20 wherein each register set includes an address register for holding an address pointer, a result register for storing data read from the specified address, and a data register for storing the data to be written to the address.
22. The atomic instruction emulator of claim 21 wherein the request comprises separate commands specifying operations to be performed on the register set assigned to the processor.
23. The atomic instruction emulator of claim 22 wherein the request includes a write command to write data to the data register, a write address command to write an address pointer to the address register, and a read command to read the results register.
24. An atomic instruction emulator system, comprising:
a bus that supports an atomic instruction;
at least one master device coupled to the bus that supports the atomic instruction;
at least one master device coupled to the bus that does not support the atomic instruction;
a slave resource coupled to the bus that is shared by the master devices; and
a hardware emulator for emulating the atomic instruction for the master device that does not support the atomic instruction, the emulator including,
a queue for queuing multiple incoming emulation requests from the master devices that do not support the atomic instruction, each request specifying an address within the shared resource and data to write to that address,
N register sets, assigned to respective masters on the bus that do not support the atomic instruction, each register set for storing the address and data from the request received from the respective master device, and
a state machine for performing the atomic instruction on behalf of the requesting master device using the address and data stored in the corresponding register set.
25. The system of claim 24 wherein the emulator further includes a slave control and master control for interfacing with the bus.
26. The system of claim 25 wherein each register set includes an address register for holding an address pointer, a result register for storing data read from the specified address, and a data register for storing the data to be written to the address.
27. The system of claim 26 wherein the request comprises separate commands specifying operations to be performed on the register set assigned to the processor.
28. The system of claim 27 wherein the request includes a write command to write data to the data register, a write address command to write an address pointer to the address register, and a read command to read the results register.