Method of bypassing a plurality of clock trees in EDA tools
A method for using timing simulation and authentication software of an EDA tool (electronics design automatic tool) to bypass a plurality of clock trees in the EDA tool. The EDA tool contains a plurality of clocking devices that prevent the timing simulation and authentication software from changing an order of the plurality of clocking devices. The method includes measuring a delay time of the clocking device, and providing a first buffer, which is electrically connected to the clocking device, according to the delay time, wherein the delay time of the first buffer approximates the delay time of the clocking device.
1. A method for using timing simulation and authentication software of an EDA tool (electronics design automatic tool) to bypass a plurality of clock trees in the EDA tool, the EDA tool comprising a plurality of clocking devices that prevent the timing simulation and authentication software from changing an order of the plurality of clocking devices, the method comprising:
measuring a delay time of the clocking device;
providing a first buffer, which is electrically connected to the clocking device, wherein the delay time of the first buffer approximates the delay time of the clocking device;
connecting a clock input port of the first buffer to a clock input port of the clocking device;
connecting a clock output port of the first buffer and a clock output port of the clocking device to a multiplexer; and
controlling the multiplexer to output a clock signal transmitted from the first buffer when executing the timing simulation and authentication software.
2. The method of claim 1 further comprising connecting a second buffer to a clock input port of the first buffer and a clock input port of the clocking device in order to ensure a distance between the second buffer and the first buffer approximates a distance between the second buffer and the clocking device.
3. The method of claim 1 wherein the timing simulation and authentication software comprises a static timing analyzer (STA).
4. The method of claim 1 wherein the EDA tool further comprises an electric circuit layout auto-creation program, and the first buffer is generated by the electric circuit layout auto-creation program.
5. The method of claim 1 wherein the clocking device comprises a flip-flop.