Double-data rate phase-locked-loop with phase aligners to reduce clock skew

1. A phase-aligning phase-locked loop (PLL) comprising:

a phase-frequency detector having a reference input and a feedback input, for determining phase differences between the reference input and the feedback input;

a loop filter for generating a control voltage;

a charge pump, controlled by the phase-frequency detector, for charging and discharging the loop filter to adjust the control voltage;

a voltage-controlled oscillator (VCO) generating multi-phase output clocks having an output frequency controlled by the control voltage from the loop filter;

an analog divider, receiving at least two of the multi-phase output clocks from the VCO, and generating a divided analog feedback clock having a feedback frequency that is the output frequency divided by a positive power of two;

a clock buffer, receiving the divided analog feedback clock, for generating a digital feedback clock;

a feedback digital divider, receiving the digital feedback clock, for generating a final feedback clock having a final feedback frequency that is the feedback frequency divided by a positive power of two; and

a feedback flip-flop, receiving the final feedback clock and clocked by the digital feedback clock, for generating a phase-aligned feedback clock to the feedback input of the phase-frequency detector;

whereby the analog divider and digital divider are in a feedback path.

2. The phase-aligning phase-locked loop of claim 1 further comprising:

a reference digital divider, receiving a reference clock having a reference frequency, for generating a final reference clock having a final reference frequency that is the reference frequency divided by a positive power of two;

a reference flip-flop, receiving the final reference clock and clocked by the reference clock, for generating a phase-aligned reference clock to the reference input of the phase-frequency detector.

3. The phase-aligning phase-locked loop of claim 2 wherein the feedback digital divider comprises a first cascade of digital dividers in series, each of the digital dividers dividing by two or a power of two.

4. The phase-aligning phase-locked loop of claim 3 wherein the reference digital divider comprises a second cascade of digital dividers in series, each of the digital dividers dividing by two or a power of two;

wherein the first cascade of dividers divides by a same divisor as the second cascade of dividers; whereby the reference clock and the digital feedback clock are divided by a same divisor.

5. The phase-aligning phase-locked loop of claim 4 wherein each digital divider is a flip-flop clocked by an output of an upstream digital divider or by the digital feedback clock.

6. The phase-aligning phase-locked loop of claim 5 wherein each digital divider is a D-type flip-flop having a D input receiving a Q-bar signal from within the digital divider.

7. The phase-aligning phase-locked loop of claim 2 wherein the analog divider is a source-coupled-logic SCL divider.

8. The phase-aligning phase-locked loop of claim 7 wherein the multi-phase output clocks are coupled to inputs of the analog divider through capacitors to gates of dynamic-load transistors of cross-coupled flip-flops.

9. The phase-aligning phase-locked loop of claim 2 wherein the feedback flip-flop is a D-type flip-flop with a D-input receiving the final feedback clock;

wherein the reference flip-flop is a D-type flip-flop with a D-input receiving the final reference clock.

10. The phase-aligning phase-locked loop of claim 2 wherein the VCO is an inductance-capacitance LC oscillator having four in-phase and quadrature-phase output clocks that are offset from each other by 90 degrees.

11. The phase-aligning phase-locked loop of claim 10 wherein the VCO comprises:

a first LC oscillator having:

a first true inductor and a first complement inductor;

a first pair of cross-coupled transistors including a first true cross transistor connected to the first true inductor and a first complement cross transistor connected to the first complement inductor;

a first current source coupled to the first pair of cross-coupled transistors;

a second LC oscillator having:

a second true inductor and a second complement inductor;

a second pair of cross-coupled transistors including a second true cross transistor connected to the second true inductor and a second complement cross transistor connected to the second complement inductor;

a second current source coupled to the second pair of cross-coupled transistors;

a first true coupling transistor, having a gate connected to the second true inductor and the second true cross transistor;

a first complement coupling transistor, having a gate connected to the second complement inductor and the second complement cross transistor;

a first adjustable source transistor, coupled to sources of the first true coupling transistor and the first complement coupling transistor and having a gate controlled by a bias voltage;

a second true coupling transistor, having a gate connected to the second true inductor and the second true cross transistor;

a second complement coupling transistor, having a gate connected to the first complement inductor and the first complement cross transistor;

a second adjustable source transistor, coupled to sources of the first true coupling transistor and the first complement coupling transistor and having a gate controlled by the bias voltage; and

a bias-voltage generator, receiving the control voltage from the loop filter, for generating the bias voltage.

12. The phase-aligning phase-locked loop of claim 11 wherein the bias-voltage generator comprises:

a p-channel bias transistor having a gate that receives the control voltage;

an n-channel bias transistor having a gate that receives the control voltage;

wherein drains of the p-channel bias transistor and the n-channel bias transistor are connected together to generate the bias voltage.

13. The phase-aligning phase-locked loop of claim 12 wherein a substrate terminal of the p-channel bias transistor is driven by a n-channel bulk transistor.

14. The phase-aligning phase-locked loop of claim 2 wherein the final feedback frequency is no more than one-sixteenth of the feedback frequency.

15. The phase-aligning phase-locked loop of claim 14 wherein the digital feedback clock has the feedback frequency.

16. The phase-aligning phase-locked loop of claim 15 wherein the charge pump is a dual-path charge pump driving a dual loop filter.

17. A phase-locked loop (PLL) comprising:

a phase-frequency detector with a reference input and a feedback input;

a feedback flip-flop having a feedback data input and a feedback clock input, for driving the feedback input to the phase-frequency detector;

a loop filter for generating a control voltage;

a charge pump, activated by the phase-frequency detector, for driving the loop filter;

a quadrature voltage-controlled oscillator (VCO), coupled to the control voltage, generating four phases of an output clock having an output frequency;

an analog divider receiving two of the four phases of the output clock, and generating an analog feedback clock;

a buffer receiving the analog feedback clock, and driving a feedback clock input to the feedback flip-flop;

a feedback series of digital flip-flops for driving the feedback data input to the feedback flip-flop, and coupled to the buffer;

a reference flip-flop having a reference data input and a reference clock input, for driving the reference input to the phase-frequency detector;

a reference series of digital flip-flops for driving the reference data input to the reference flip-flop, and coupled to a reference clock.

18. The PLL of claim 17 wherein the analog divider comprises:

a first analog flip-flop having a first pair of source transistors and a first sink transistor;

a second analog flip-flop having a second pair of source transistors and a second sink transistor;

wherein the first and second analog flip-flops are cross-coupled;

a first voltage divider, receiving a high bias voltage and a low bias voltage and a first phase clock being one of the two of the four phases of the output clock received from the quadrature voltage-controlled oscillator, having a first capacitor between the first phase clock and gates of the second pair of source transistors and a second capacitor between the first phase clock and a gate of the first sink transistor, and a first resistor between the low bias voltage and the first capacitor and a second resistor between the high bias voltage and the second capacitor; and

a second voltage divider, receiving the high bias voltage and the low bias voltage and a second phase clock being one of the two of the four phases of the output clock received from the quadrature voltage-controlled oscillator, having a third capacitor between the second phase clock and gates of the first pair of source transistors and a fourth capacitor between the second phase clock and a gate of the second sink transistor, and a third resistor between the high bias voltage and the third capacitor and a fourth resistor between the low bias voltage and the fourth capacitor.

19. A phase-aligner phase-locked loop (PLL) comprising:

phase-frequency detect means, having a reference input and a feedback input, for comparing phases of clocks applied to the reference input and to the feedback input;

feedback flip-flop means, having a feedback data input and a feedback clock input, for driving the feedback input to the phase-frequency detect means;

loop filter means for generating a control voltage;

charge pump means, activated by the phase-frequency detect means, for driving the loop filter means;

quadrature voltage-controlled oscillator means for generating four phases of an output clock having an output frequency in response to the control voltage;

analog divider means, receiving two of the four phases of the output clock, for generating an analog feedback clock;

buffer means, receiving the analog feedback clock, for driving a feedback clock input to the feedback flip-flop means;

feedback series means for driving the feedback data input to the feedback flip-flop means with a divided-down frequency clock, and coupled to the buffer means;

reference flip-flop means, having a reference data input and a reference clock input, for driving the reference input to the phase-frequency detect means;

reference series means for driving the reference data input to the reference flip-flop means with a divided-down frequency clock, and coupled to a reference clock.

20. The phase-aligner phase-locked loop of claim 19 wherein delays through the feedback series means matches delays through the reference series means;

wherein delays through the feedback flip-flop means matches delays through the reference flip-flop means.