High-speed segmented data bus architecture

1. A system for driving data signals in an integrated circuit device comprising:

a plurality of functional blocks, each functional block having at least one input/output connection along one side of the integrated circuit device;

a data bus comprising a plurality of electrically independent segments, each segment spanning a respective portion of the one side of the integrated circuit device;

a plurality of lines electrically coupling the input/output connections of the functional blocks to the segments of the data bus, wherein the lines are grouped into a plurality of subsets, and each subset is electrically coupled to a different segment of the data bus;

a charging circuit coupled to each of the data bus segments, wherein the charging circuit is configured to charge the data bus segment to a first voltage level; and

a pull-down circuit coupled to each of the data bus segments, wherein the pull-down circuit is configured to pull the data bus to a second voltage level.

2. The system of claim 1 , wherein each charging circuit comprises:

a transistor coupled at one end to a power supply and at another end to the respective segment of the data bus, wherein the transistor is controlled by an equilibration signal.

3. The system of claim 1 , wherein the pull-down circuit comprises:

a transistor coupled at one end to the respective segment of the data bus and at another end to ground; and

logic circuitry coupled to the input/output connections for controlling the transistor.

4. The system of claim 3 , wherein the logic circuitry comprises a first input terminal for receiving an equilibration signal and a second input terminal for receiving a data signal.

5. The system of claim 3 , wherein the logic circuitry comprises a NOR gate.

6. The system of claim 3 , wherein the logic circuitry comprises an inverter gate.