Wiring modeling technique

1. In a semiconductor device having wirings, a wiring modeling technique comprising the steps of selecting an arbitrary region of said semiconductor device; calculating a wiring area ratio of said wirings to said region; and determining said region and said wiring area ratio to model the cross-sectional profile of a target wiring located in the middle of said region.

2. The wiring modeling technique according to claim 1 , wherein if said wiring area ratio varies with changes of said region in a certain direction when said region is uniformly expanded or reduced by a predetermined distance with said target wiring located at the center, an intermediate value between the maximum and the minimum of said wiring area ratio with respect to said predetermined distance is determined as a wiring area ratio of said target wiring and a region corresponding to said wiring area ratio of said target wiring is determined as a region for said target wiring.

3. In a semiconductor device having wirings, a wiring modeling technique comprising the steps of dividing said wirings into a plurality of wiring regions on said semiconductor device; calculating a wiring area ratio of wirings contained in each of said wiring regions to said wiring region; and determining said plurality of wiring regions and the wiring area ratios corresponding to said plurality of wiring regions to model the cross-sectional profile of wirings contained in each of said plurality of wiring regions.

4. In a semiconductor device having wirings, a wiring modeling technique comprising the steps of selecting a rectangular region of said semiconductor device to limit wirings contained in said rectangular region; calculating a wiring area ratio of said wirings to said rectangular region; and determining said rectangular region and said wiring area ratio to model the cross-sectional profile of wirings contained in said rectangular region.

5. In a semiconductor device having wirings, a wiring modeling technique comprising the steps of limiting a wiring of said semiconductor device as a target wiring; confining a certain rectangular region with a target wiring portion on said target wiring being located at the center thereof; calculating a wiring area ratio of wirings contained in said rectangular region to said rectangular region; determining said rectangular region and said wiring area ratio to model the cross-sectional profile of said target wiring portion; subsequently confining said certain rectangular region with another target wiring portion at a predetermined distance from the target wiring portion on said target wiring being located at the center thereof; calculating a wiring area ratio of wirings contained in said rectangular region to said rectangular region; determining said rectangular region and said wiring area ratio to model the cross-sectional profile of said another target wiring portion; repeating said modeling operation for each portion at said predetermined distance on said target wiring to complete a one-dimensional modeling operation for said target wiring; repeating, for an adjacent target wiring next to said target wiring, the same modeling operation as the one-dimensional modeling operation for said target wiring to complete a one-dimensional modeling operation for said adjacent target wiring; and performing said one-dimensional modeling operation on all wirings to complete a two-dimensional modeling operation for the wirings of said semiconductor device.

6. The wiring modeling technique according to claim 4 or 5 , wherein said rectangular region has an area between 10 μm 2 and 10 mm 2 .