Single ended tuning of a differential power amplifier output
View Patent ↗A system and method for compensating a parasitic capacitance on a differential amplifier output includes a first differential output and a second differential output of the differential amplifier. The first differential output coupled to the second differential output by a first conductor that has a length of about one half wavelength. The first and the second differential outputs have a parasitic capacitance that can be measured. A second conductor is coupled to the first differential output. The second conductor having a length that is less than or equal to about one quarter wavelength and has an inductive reactance that offsets a capacitive reactance of the parasitic capacitance.
1. A transmitter output circuit comprising:
a first and a second differential outputs of a PA, the first differential output coupled to the second differential output by a first conductor that has a length of about a multiple of one half wavelength, the first and the second differential outputs having a parasitic capacitance;
a second conductor that is coupled to the first differential output, the second conductor having a length that is less than or equal to about one quarter wavelength plus a multiple of one half wavelength, the second conductor having an inductive reactance that offsets a capacitive reactance of the parasitic capacitance, the second conductor includes a DC bias network.
2. The circuit of claim 1 , wherein the first conductor that has a length of about a multiple of one half wavelength can include a length of about one half wavelength.
3. The circuit of claim 1 wherein, the second conductor having a length that is equal to or less than about one quarter wavelength plus a multiple of one half wavelength can include a length that is equal to or less than about one quarter wavelength.
4. The circuit of claim 1 , wherein the first conductor is formed such that a signal cross coupling between portions of the first conductor is minimized.
5. The circuit of claim 1 , wherein the second conductor is formed such that a signal cross coupling between portions of the second conductor is minimized.
6. The circuit of claim 1 , wherein the first conductor and the second conductor are separated such that a signal cross coupling between the first conductor and the second conductor is minimized.
7. The circuit of claim 1 , further comprising a balun including:
a primary portion that includes the first conductor; and
a secondary portion including:
a third conductor; and
a fourth conductor, the third conductor and the fourth conductor having a length equal to about one quarter wavelength, the fourth conductor being coupled between a ground potential and an antenna port, the third conductor and the fourth conductor being substantially aligned with the first conductor so as to maximize a signal cross coupling from the first conductor to the third conductor and the fourth conductor.
8. The circuit of claim 7 , wherein the balun is formed in a structure that includes a plurality of layers.
9. The circuit of claim 8 , wherein the first conductor is formed on a first layer of the plurality of layers and the third conductor and the fourth conductor are formed on a second layer of the plurality of layers and a insulating third layer of the plurality of layers separates the first layer and the second layer.
10. The circuit of claim 7 , wherein the balun is formed in a coupled line structure.
11. The circuit of claim 1 , wherein the transmitter output circuit is included in a package.
12. The circuit of claim 11 , wherein the package is an LTCC package.
13. A DC bias network for supplying bias current to a differential amplifier comprising:
a first conductor, the first conductor being coupled between a DC bias source and a first output of the differential amplifier, a second output of the differential output being coupled to the first output by a second conductor having a length of about one half wavelength plus a multiple of one half wavelength, the first conductor having a length of about one quarter wavelength plus a multiple of one half wavelength and an inductive reactance equal to a parasitic capacitive reactance on the first output and the second output of the differential amplifier, the first conductor includes the DC bias network.
14. The DC bias network of claim 13 , wherein the DC bias network is included in a package, the package including an amplifier output circuit.
15. The DC bias network of claim 14 , wherein the second conductor having a length of about one half wavelength plus a multiple of one half wavelength can include a length of about one half wavelength.
16. The DC bias network of claim 13 , wherein the first conductor having a length of about one quarter wavelength plus a multiple of one half wavelength can include a length of one quarter wavelength.
17. A method of compensating for a parasitic capacitance on a differential amplifier output comprising: coupling a first differential output of the differential amplifier to a second differential output of the differential amplifier with a first conductor having a length of about one half wavelength plus a multiple of one half wavelength; and coupling a second conductor to the first differential output of the differential amplifier, the second conductor having a length of about one quarter wavelength plus a multiple of one half wavelength and an inductive reactance equal to a parasitic capacitive reactance on the first output and the second output of the differential amplifier, the second conductor includes a DC bias network.
18. The method of claim 17 , wherein the first conductor that has a length of about one half wavelength plus a multiple of one half wavelength can include a length of about one half wavelength.
19. The method of claim 17 , wherein the second conductor having a length of about one quarter wavelength plus a multiple of one half wavelength can include a length of about one quarter wavelength.