Electronic package with optimized lamination process
View Patent ↗An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T 1MIN and a maximum temperature T 1MAX . T 1MAX constrains the ductility of the first dielectric layer to be at least D 1 following the laminating. T 1MAX depends on D 1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T 2MIN and a maximum temperature T 2MAX . T 2MAX constrains the ductility of the second dielectric layer to be at least D 2 following the laminating. T 2MAX depends on D 2 and on a second dielectric material comprised by the second dielectric layer.
1. A method of making a multi-layered interconnect structure, comprising the steps of:
providing a thermally conductive layer including first and second opposing surfaces;
laminating a first dielectric layer on said first opposing surface of said thermally conductive layer such that the first dielectric layer includes a first dielectric material, said laminating occurring at a pressure between a minimum pressure of about P 1MIN and a maximum pressure of about P 1MAX and at a temperature between a minimum temperature of about T 1MIN and a maximum temperature of about T 1MAX , wherein T 1MAX constrains a ductility of the first dielectric layer to be at least about D 1 following said laminating, and wherein T 1MAX depends on D 1 and on the first dielectric material; and
laminating a second dielectric layer on said second opposing surface of said thermally conductive layer such that the second dielectric layer includes a second dielectric material, said laminating occurring at a pressure between a minimum pressure of about P 2MIN and a maximum pressure of about P 2MAX and at a temperature between a minimum temperature of about T 2MIN and a maximum temperature of about T 2MAX , wherein T 2MAX constrains a ductility of the second dielectric layer to be at least about D 2 following said laminating, and wherein T 2MAX depends on D 2 and on the second dielectric material.
2. The method of claim 1 , wherein D 1 =8%, and wherein D 2 =8%.
3. The method of claim 1 , wherein D 1 =100%, and wherein D 2 =100%.
4. The method of claim 1 , wherein the first dielectric material comprises silica filled polytetrafluoroethylene, wherein P 1MIN =1000 psi, wherein P 1MAX =3000 psi, wherein T 1MIN =670° F., and wherein T 1MAX =695° F., wherein the second dielectric material comprises silica filled polytetrafluoroethylene, wherein P 2MIN =1000 psi, wherein P 2MAX =3000 psi, wherein T 2MIN =670° F., and wherein T 2MAX =695° F.
5. The method of claim 1 , further comprising:
forming first and second pluralities of electrically conductive members on said first and second dielectric layers, respectively;
forming a first electrically conductive layer within said first dielectric layer;
forming a second electrically conductive layer within said first dielectric layer and positioned between said first electrically conductive layer and said thermally conductive layer, wherein said second electrically conductive layer comprises a first plurality of shielded signal conductors;
forming a plated through hole through the multi-layered interconnect structure electrically connected to at least one member of said first plurality of electrically conductive members, to at least one of said first plurality of shielded signal conductors, and to at least one member of said second plurality of electrically conductive members; and
forming a third dielectric layer on said first dielectric layer and on portions of said first plurality of electrically conductive members, said third dielectric layer substantially overlying said plated through hole, and wherein said third dielectric layer includes a first high density interconnect layer for providing an electrical path from a first electronic device to the first plurality of shielded signal conductors.
6. The method of claim 5 , wherein said third dielectric layer includes a resin comprising an allylated polyphenylene ether.
7. The method of claim 1 , wherein T 2MIN =T 1MIN and T 2 MAX =T 1MAX , and wherein the method further comprises heating the first and second dielectric layers on said first and second opposing surfaces, respectively of said thermally conductive layer in a heatup stage from ambient room temperature to the temperature between about T 1MIN and about T 1MAX in temperature increments that are sufficiently small that spatial temperature uniformity is achieved in said first and second dielectric layers for each said temperature increment.
8. The method of claim 7 , wherein T 1MIN =670° F. and T 1MAX =695° F.
9. The method of claim 8 , wherein said temperature increments are each 2° F.
10. The method of claim 8 , wherein the heatup stage has a duration of 42 minutes to 57 minutes.
11. The method of claim 8 , further comprising after the heatup stage: maintaining the structure at an approximately constant temperature between about T 1MIN and about T 1MAX in a dwell stage.
12. The method of claim 11 , wherein the dwell stage has a duration of 105 minutes to 125 minutes.
13. The method of claim 11 , further comprising after the heatup stage: cooling the structure to 400° F. in a slow cool stage followed by cooling the structure from 400° F. to ambient room temperature in a rapid cool stage.
14. The method of claim 13 , wherein the slow cool stage has a duration of 120 minutes to 150 minutes, and wherein the rapid cool stage has a duration of less than 180 minutes.