Method and architecture for synchronizing a path generator and/or extractor to a processor

1. A method for synchronizing an overhead generator or an overhead extractor to an overhead processor having a combined path and transport overhead interface, comprising the steps of:

(A) synchronizing overhead data with a pulse generated in a first row; and

(B) presenting the overhead data in the first row, wherein the overhead data is processed in a subsequent row.

2. The method according to claim 1 , wherein:

the pulse comprises a start of frame pulse; and

the overhead data comprises at least one transport overhead byte.

3. The method according to claim 1 , wherein:

the pulse comprises a start of payload pulse; and

the overhead data comprises at least one path overhead byte.

4. The method according to claim 1 further comprising the steps of:

communicating a start of frame pulse via a first pin;

communicating a start of payload pulse via a second pin; and

multiplexing transport overhead data and path overhead data on a third pin.

5. The method of claim 1 , further comprising the step of:

communicating at least one out-of-synchronization condition with the pulse by in-band signaling.

6. The method according to claim 5 , wherein the in-band signaling comprises embedding one or more patterns in the pulse.

7. The method of claim 1 , further comprising the steps of:

determining when the pulse occurs relative to an expected time; and

synchronizing the overhead data based on the result of the determining step.

8. A circuit having a combined path overhead and transport overhead interface comprising:

means for synchronizing overhead data with a pulse generated in a first row; and

means for presenting the overhead data in the first row, wherein the overhead data is processed in a subsequent row.

9. An apparatus comprising:

a first pin at which a pulse is presented;

a second pin at which overhead data is presented; and

an interface circuit combining path overhead interface features and transport overhead interface features into a single interface, wherein said interface circuit is configured to synchronize the overhead data with the pulse, wherein the pulse is generated in a first row and the overhead data is presented in the first row and processed in a subsequent row.

10. The apparatus according to claim 9 , wherein:

the pulse comprises a start of frame pulse; and

the overhead data comprises at least one transport overhead byte.

11. The apparatus according to claim 9 , wherein:

the pulse comprises a start of payload pulse; and

the overhead data comprises at least one path overhead byte.

12. The apparatus according to claim 9 , further comprising a third pin, wherein:

a start of frame pulse is presented at the first pin;

a start of payload pulse is presented at the third pin; and

said interface circuit is configured to multiplex transport overhead data and path overhead data on the second pin.

13. The apparatus according to claim 12 , wherein:

the interface circuit is further configured to communicate at least one out-of-synchronization condition via the start of payload pulse by in-band signaling.

14. The apparatus according to claim 12 , wherein:

the interface circuit is further configured to communicate at least one out-of-synchronization condition by embedding one or more patterns in the start of payload pulse.

15. The apparatus according to claim 12 , wherein:

the interface circuit is further configured (i) to compare when the start of payload pulse occurs to an expected time and (ii) to synchronize the path overhead data based on a result of the comparison.

16. The apparatus according to claim 12 , further comprising:

a fourth pin at which a clock signal is presented, wherein the interface circuit is further configured to shift the overhead data in response to the clock signal.

17. The apparatus according to claim 12 , wherein the apparatus comprises one or more of an overhead processor, an overhead generator and an overhead extractor.

18. The apparatus according to claim 12 , wherein the apparatus comprises:

a first interface circuit configured to de-multiplex transport and path overhead data received from an overhead generator; and

a second interface circuit configured to multiplex transport and path overhead data presented to an overhead extractor.

19. The apparatus according to claim 15 , wherein said interface circuit is configured to count a number of clock cycles occurring between start of payload pulses.

20. The apparatus according to claim 19 , wherein said interface circuit is configured to generate:

in-band signaling to indicate a negative frequency justification condition when the start of payload pulse occurs earlier than expected; and

in-band signaling to indicate a positive frequency justification condition when the start of payload pulse occurs later than expected.