Patent Assignment
Reel/Frame 031950/0752
Assignment of Assignor's Interest
Recorded: 2014-01-09
Pages: 27
Assignor
CYPRESS SEMICONDUCTOR CORPORATION
Executed: 2013-12-18
Assignee
RPX CORPORATION
ONE MARKET PLAZA, STEUART TOWER, SUITE 800, SAN FRANCISCO, CALIFORNIA, 94105
Covered Properties
(135)
Electrostatic Discharge (Esd) Protection Circuit and Structure for Output Drivers
Patent:
5,623,156 →
Application:
08/535,426 →
Adaptive Equalizer Circuit Including Multiple Equalizer Units
Patent:
5,670,916 →
Application:
08/549,373 →
Programmably Timed Storage Element for Integrated Circuit Input/Output
Patent:
6,167,528 →
Application:
08/576,081 →
Memory in a Programmable Logic Device
Patent:
5,804,986 →
Application:
08/580,626 →
Atm Receiver
Patent:
6,028,844 →
Application:
08/599,509 →
Phase Independent Receiver and/or Decoder
Patent:
6,385,745 →
Application:
08/885,333 →
Peak Detector Circuit with Extended Input Voltage Range
Patent:
6,084,439 →
Application:
08/886,913 →
Correctable Output Driver and Method of Using the Same
Patent:
5,994,923 →
Application:
08/947,250 →
Circuit, Apparatus and Method for Generating Signals Phase-Separated by Ninety Degrees
Patent:
6,052,010 →
Application:
08/957,725 →
Multi-Speed Retainer
Patent:
6,097,738 →
Application:
08/966,938 →
Architecture for a Dual Segment Dual Speed Repeater
Patent:
6,195,360 →
Application:
08/970,058 →
Circuits and Methods for Framing One or More Data Streams
Patent:
5,960,007 →
Application:
08/975,644 →
Circuits and Methods for Framing One or More Data Streams
Patent:
5,982,786 →
Application:
08/976,072 →
Distributed Port Select Method for a Multi-Segment Repeater
Patent:
6,115,364 →
Application:
08/976,410 →
Structure and Process for a Gouge-Free Stacked Non-Volatile Memory Cell with Select Gate
Patent:
6,162,682 →
Application:
09/010,893 →
Roving Range Control to Limit Receive Pll Frequency of Operation
Patent:
5,952,888 →
Application:
09/047,595 →
Framer Method Architecture and Circuit with Programmable Symbol Selection
Patent:
6,763,036 →
Application:
09/275,625 →
Low Latency, Low Power Deserializer
Patent:
6,265,996 →
Application:
09/301,900 →
Low Latency, Low Power Deserializer
Patent:
6,535,527 →
Application:
09/302,193 →
One-Shot Pulse Synchronizer
Patent:
6,218,874 →
Application:
09/327,835 →
Circuit, Method and/or Architecture for Improving the Performance of a Serial Communication Link
Patent:
6,625,177 →
Application:
09/370,262 →
Circuit, Method and/or Architecture for Improving the Performance of a Serial Communication Link
Patent:
6,628,656 →
Application:
09/371,051 →
An Apparatus Comprising of a Frequency Difference Detector with a User Selectable or Programmable Channel Count Configuration
Patent:
6,513,127 →
Application:
09/405,626 →
Overhead Serial Communication Scheme
Patent:
6,665,265 →
Application:
09/435,749 →
Method and Architecture for Synchronizing a Transport and Path Overhead Generator and/or Extractor to an Overhead Transport and Path Processor
Patent:
6,502,197 →
Application:
09/436,314 →
Data Transmitter with Sequential Serialization
Patent:
6,665,360 →
Application:
09/466,652 →
Digital Phase/Frequency Detector, and Clock Generator and Data Recovery Pll Containing the Same
Patent:
6,683,930 →
Application:
09/470,665 →
Reference-Free Clock Generation and Data Recovery Pll
Patent:
6,310,521 →
Application:
09/471,576 →
Reference- Free Clock Generator and Data Recovery Pll
Patent:
6,307,413 →
Application:
09/471,914 →
Data Frequency Detector
Patent:
6,366,135 →
Application:
09/471,915 →
Apparatus and Protocol for Detected Error Propagation in Serial-Transport Block-Coded Interfaces
Patent:
6,886,126 →
Application:
09/534,108 →
Signal Line Matching Technique for Ics/Pcbs
Patent:
6,573,757 →
Application:
09/658,598 →
Logic Gate with Symmetrical Propagation Delay from Any Input to Any Output and a Controlled Output Pulse Width
Apparatus and Protocol for Exception Propagation in Serial Transport Block Coded Interfaces
Patent:
7,016,430 →
Application:
09/814,194 →
Communication Protocol for the Broadcast of First/Last Event Detection Over a Single Communication Channel
Patent:
7,103,071 →
Application:
09/822,979 →
Independently Roving Range Control
Patent:
6,885,714 →
Application:
09/865,208 →
Multi-Phase Voltage-Controlled Oscillator Operable at Modulated, Operating Frequency
Patent:
6,690,243 →
Application:
09/878,074 →
Clock Circuit with Self Correcting Duty Cycle
Patent:
6,518,809 →
Application:
09/920,029 →
Apparatus and Method for Integrating an Optical Transceiver with a Surface Mount Package
Patent:
6,592,269 →
Application:
09/944,856 →
Circuit and Method for Adjusting Duty Cycle of a High Speed, Low Swing Output Signal
Patent:
6,762,636 →
Application:
10/014,680 →
Technique for Multiprotocol Transport Using Mpls (Multi-Protocol Label Switching)
Patent:
7,161,946 →
Application:
10/021,992 →
System and Method for Controlling the Frequency Output from an Oscillator Using an in-Phase Voltage
Patent:
6,667,668 →
Application:
10/042,782 →
Method and Architecture for Self-Clocking Digital Delay Locked Loop
Parallel Framer and Transport Protocol with Distributed Framing and Continuous Data
Patent:
6,539,051 →
Application:
10/096,056 →
Dual Differential Input Comparators with Integrated Phase Detector
Patent:
6,617,883 →
Application:
10/106,701 →
System and Method for Generating Interleaved Multi-Phase Outputs from a Nested Pair of Phase Locked Loops
Patent:
6,657,466 →
Application:
10/154,030 →
Triple Input Phase Detector and Methodology for Setting Delay Between Two Sets of Phase Outputs
Patent:
6,774,689 →
Application:
10/154,031 →
Optical Switch Cascading System and Method with Variable Incidence Angle Correction
Patent:
6,853,762 →
Application:
10/155,748 →
Cascading Optical Switch Multi-Plane System and Method
Patent:
6,983,087 →
Application:
10/155,774 →
Optical Switch Cascading System and Method with Fixed Incidence Angle Correction
Patent:
7,013,058 →
Application:
10/155,780 →
Out of Band Communications Link for 4-Lane Optical Modules Using Dark Fibers and Low-Bandwidth Leds
Patent:
7,062,177 →
Application:
10/183,812 →
Method and Apparatus for Configuring Signal Lines According to Idle Codes
Patent:
7,301,961 →
Application:
10/209,142 →
Multi-Bit Deskewing of Bus Signals Using a Training Pattern
Patent:
7,036,037 →
Application:
10/218,239 →
Parallel Data Interface and Method for High-Speed Timing Adjustment
Patent:
7,069,458 →
Application:
10/222,129 →
Cascading Optical Switch Three Dimensional Switch Fabric System and Method
Patent:
6,870,982 →
Application:
10/226,460 →
Error Monitoring System and Method
Patent:
7,036,070 →
Application:
10/246,952 →
Method and Architecture for Synchronizing a Path Generator and/or Extractor to a Processor
Patent:
7,334,147 →
Application:
10/254,103 →
High Speed on-Chip Signaling System and Method
Patent:
6,727,730 →
Application:
10/256,416 →
Method and Apparatus for Framing a Data Packet
Patent:
7,283,565 →
Application:
10/264,684 →
Method and System for High Resolution Delay Lock Loop
Patent:
6,710,636 →
Application:
10/264,692 →
Electro-Optical Apparatus
Patent:
6,815,729 →
Application:
10/268,200 →
Method of Manufacturing Electro-Optical Devices
Patent:
6,892,449 →
Application:
10/268,205 →
Electro-Optical Apparatus
Patent:
6,890,107 →
Application:
10/268,216 →
Methods of Improving Reliability of an Electro-Optical Module
Patent:
7,129,722 →
Application:
10/268,275 →
Clock Data Recovery Method and Circuit for Network Communication
Patent:
7,158,601 →
Application:
10/282,498 →
Low Voltage Differential Signal Driver Circuit and Method
Patent:
6,900,663 →
Application:
10/288,003 →
Low Voltage Receiver Circuit and Method for Shifting the Differential Input Signals of the Receiver Depending on a Common Mode Voltage of the Input Signals
Patent:
6,768,352 →
Application:
10/293,392 →
Method and System of Cycle Slip Framing in a Deserializer
Patent:
7,372,928 →
Application:
10/295,736 →
Method and Apparatus for Aggregating Ethernet Streams
Patent:
7,382,805 →
Application:
10/315,581 →
Method and Apparatus for Assembling Non-Aligned Packet Fragments Over Multiple Cycles
Method and Apparatus for Separation of Control and Data Packets
Patent:
7,843,922 →
Application:
10/325,555 →
Method and Apparatus for the Deletion of Bytes When Performing Byte Rate Adaptation
Patent:
7,356,044 →
Application:
10/327,224 →
Method and Apparatus for Assembly of Virtually Concatenated Data
Patent:
7,493,392 →
Application:
10/327,232 →
Method and Apparatus for Introducing Differential Delay Between Virtually Concatenated Tributaries
Patent:
7,324,562 →
Application:
10/327,250 →
Method and Apparatus for a Multi-Channel High Speed Framer
Patent:
7,069,407 →
Application:
10/327,456 →
Device Identification Method for Systems Having Multiple Device Branches
Patent:
7,073,018 →
Application:
10/331,673 →
Low Power Deserializer Circuit and Method of Using Same
Patent:
6,696,995 →
Application:
10/334,098 →
Logic for Implementing a Dual Clock Domain Read Access with Predictable Timing for Bi-Directional Inputs/Outputs
Patent:
7,934,057 →
Application:
10/746,349 →
Method of Maximizing Bandwidth Efficiency in a Protocol Processor
Patent:
7,496,109 →
Application:
10/777,286 →
Cyclical Redundancy Check Using Nullifiers
Patent:
7,290,196 →
Application:
10/802,519 →
Method and System for a Feed-Forward Encoder
Patent:
7,123,173 →
Application:
10/822,183 →
Scheduling Store-Forwarding of Back-to-Back Multi-Channel Packet Fragments
Patent:
7,379,467 →
Application:
10/841,774 →
A First-in-First-Out (Fifo) Memory for Buffering Packet Fragments Through Use of Read and Write Pointers Incremented by a Unit Access and a Fraction of the Unit Access
Patent:
7,272,675 →
Application:
10/841,865 →
Low Power Serializer Circuit and Method
Patent:
7,006,021 →
Application:
10/874,719 →
Phase-Locked Loop and Delay-Locked Loop Including Differential Delay Cells Having Differential Control Inputs
Cycle Slip Framing System and Method for Selectively Increasing a Frame Clock Cycle to Maintain Related Bits Within the Same Parallel-Output Frame of a Deserializer
Patent:
6,970,115 →
Application:
10/876,985 →
Differential Receiver with Wide Input Common Mode Range and Low Duty Cycle Distortion
Patent:
7,400,173 →
Application:
10/923,419 →
Multiple Byte Data Path Encoding/Decoding Device and Method
Patent:
7,138,930 →
Application:
10/937,138 →
Method and Apparatus for Collecting Statistical Information from a Plurality of Packet Processing Blocks
Patent:
7,512,075 →
Application:
10/938,289 →
Digital-Compatible Multi-State-Sense Input
Patent:
8,085,857 →
Application:
10/947,890 →
Equalizer Circuit, Communication System, and Method That Is Adaptive to Varying Launch Amplitudes for Reducing Receiver Error
Patent:
7,620,101 →
Application:
10/950,274 →
Linearized Digital Phase-Locked Loop Method for Maintaining End of Packet Time Linearity
Patent:
7,826,581 →
Application:
10/959,259 →
Asynchronous Arbiter with Bounded Resolution Time and Predictable Output State
Patent:
7,225,283 →
Application:
11/019,702 →
Method and Circuit for Rapid Alignment of Signals
Patent:
7,295,049 →
Application:
11/088,028 →
Transmission of a Continuous Datastream Through a Re-Clocked Frame-Based Transport Network
Patent:
8,094,562 →
Application:
11/138,617 →
Impedance Matching Circuit and Method
Patent:
7,961,000 →
Application:
11/193,791 →
Recursive Range Controller
Patent:
8,073,042 →
Application:
11/403,509 →
Parallel Input/Output Self-Test Circuit and Method
High-Frequency Input Circuit
Patent:
8,093,954 →
Application:
11/439,762 →
Data Loss Protection Switch System and Method
Patent:
7,979,752 →
Application:
11/494,408 →
Variable Impedance Sense Architecture and Method
Patent:
8,036,846 →
Application:
11/540,996 →
Symmetrical Range Controller Circuit and Method
Patent:
7,920,665 →
Application:
11/541,000 →
Phase-Locked Loop Fast Lock Circuit and Method
Patent:
7,439,816 →
Application:
11/541,025 →
8-Bit to 10-Bit Encoding Method and Apparatus
Method and Circuit for Rapid Alignment of Signals
Method and Apparatus for Configuring Signal Lines According to Idle Codes
Patent:
8,073,005 →
Application:
11/986,580 →
Method and System of Cycle Slip Framing in a Deserializer
Data Loss Protection Switch System and Method
Patent:
8,381,081 →
Application:
13/109,196 →
Recursive Range Controller
Patent:
8,526,558 →
Application:
13/198,164 →
Method and Architure for Synchronizing a Path Generator and/or Extractor to a Processor
Application:
60/109,501 →
Overhead Serial Communication Scheme
Application:
60/109,505 →
Logic for implementing a dual clock domain read access with predictable timing for bi-directional I/Os
Application:
60/437,303 →
Method of maximizing bandwidth efficiency in a protocol processor
Application:
60/447,173 →
High speed CRC computation methodology for byte enable based designs using CRC nullifiers
Application:
60/456,818 →
Method and apparatus for scheduling store-forwarding of back-to-back multi-channel packet segments
Application:
60/469,379 →
First-in-first-out (FIFO) memory for buffering packet fragments
Application:
60/469,380 →
Low power serializer circuit and method
Application:
60/482,933 →
Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs
Application:
60/483,208 →
Cycle slip framing scheme
Application:
60/483,378 →
Faster 8b/10b encoding and decoding on multi-byte datapath
Application:
60/503,570 →
Differential receiver with wide input common mode range and low duty cycle distortion
Application:
60/504,185 →
Protocol to collect multi-port statistical information for updating packet performance counters through daisy chaining a plurality of packet processing blocks
Application:
60/505,243 →
Equalizer architecture
Application:
60/505,706 →
Digital-compatible multi-state-sense input
Application:
60/506,677 →
Method of rapid digital phase alignment
Application:
60/556,716 →
Method to transfer a continuous datastream across a transport network
Application:
60/583,232 →
Circuit for minimizing skew introduced by variable impedence sense code updates
Application:
60/606,194 →
Recursive range controller
Application:
60/671,388 →
Parallel input/output self-test circuit and method
Application:
60/678,300 →
High-speed input circuit and termination method
Application:
60/683,960 →
Data loss protection switch
Application:
60/702,738 →
Phase-locked loop fast lock circuit and method
Application:
60/721,668 →
Symmetrical range controller for PLLs
Application:
60/721,688 →
Variable impedance sense architecture and method
Application:
60/728,476 →
8-Bit 10-bit Encoding method and apparatus
Application:
60/833,881 →
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 17, 2013
From: KORN, THOMAS
To: CYPRESS SEMICONDUCTOR
Reel/Frame 031800/0145 →
Assignment of Assignor's Interest
Dec 17, 2013
From: KLEINE, JOHN STUART
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 031803/0118 →
Security Interest
Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
Release of Security Interest
Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →