Parallel input/output self-test circuit and method
View Patent ↗A parallel data transmission test system can include a receiver section ( 100 ) having input selector circuits ( 104 -O to 104 -N) that provide a received test data to logic adjust circuits ( 106 -O to 106 -N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit ( 108 ) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit ( 110 ).
1. A parallel data transmission test circuit, comprising:
a receiver section, comprising
a plurality of data inputs, each coupled to a corresponding a logic uniformity circuit, each logic uniformity circuit including an inverting path and non-inverting coupled between the corresponding data input and a switch circuit, the switch circuit selectively coupling the inverting path or non-inverting path to a select circuit output, and
a logic circuit that logically combines logically aligned data values to output a summarized test data value sequence; and
a transmitter section coupled to the receiver section by parallel data transmission lines, the transmitter section including, a bit pattern sequence generator circuit, and a plurality of output selector circuits that selectively output test data values onto a corresponding one of the parallel data transmission lines.
2. The parallel data transmission test circuit of claim 1 , wherein:
each output selector circuit comprises an output MUX.
3. The parallel data transmission test circuit of claim 2 , wherein:
each output MUX includes at least a first input coupled to receive a sequence of test values generated by a test sequence generator, and at least a second input coupled to receive an inverse of the sequence of test values generated by a test sequence generator.
4. The parallel data transmission test circuit of claim 3 , wherein:
the test sequence generator is a pseudo-random bit sequence generator.
5. The parallel data transmission test circuit of claim 3 , wherein:
each output MUX further includes at least a third input coupled to a first constant value generator that generates data values having a first logic value, and a fourth input coupled to a second constant value generator that generates data values having a second logic value.
6. The parallel data transmission test circuit of claim 3 , wherein:
the receiver section is formed in the substrate of a first integrated circuit; and
the transmitter section is formed in the substrate of a second integrated circuit different from the first integrated circuit.
7. The parallel data transmission test circuit of claim 3 , wherein:
the first integrated circuit comprises a content addressable memory device.