Method and apparatus for a multi-channel high speed framer

1. A framer comprising:

a first plurality of pipeline stages to frame data between a link layer and a network interface;

a first memory coupled to each pipeline stage of the first plurality of pipeline stages, the first memory to store context information at predetermined stage locations for each pipeline stage; and

a first control logic coupled to the first memory and to each pipeline stage of the first plurality of pipeline stages, the first control logic to control transfer of data between the first memory and the first plurality of pipeline stages;

and wherein each stage of the first plurality of pipeline stages is to load context information from the first memory through the first control logic and to perform a sub-function of data framing.

2. The framer of claim 1 , further comprising:

a second plurality of pipeline stages to deframe data between a link layer and a network interface each stage of the second pipeline stage to load context information from a second memory through a second control logic and to perform a sub-function of data deframing.

3. The framer of claim 2 , further comprising:

a second memory coupled to each pipeline stage of the second plurality of pipeline stages, the second memory to store context information at predetermined stage locations for each pipeline stage of the second plurality of pipeline stages.

4. The framer of claim 3 , further comprising:

a second control logic coupled to the second memory and to each pipeline stage of the second plurality of pipeline stages, the second control logic to control transfer of data between the second memory and the second plurality of pipeline stages.

5. The framer of claim 4 , further comprising:

a link layer interface coupled to the first plurality of pipeline stages and the second plurality of pipeline stages.

6. The framer of claim 5 , further comprising:

a line interface coupled to the first plurality of pipeline stages and the second plurality of pipeline stages.

7. The framer of claim 1 , wherein

the first control logic, first memory and first plurality of pipeline stages are all included in a framer; and

further comprising:

a line interface of the framer coupled to a physical link layer.

8. The framer of claim 7 , further comprising:

a link layer interface of the framer coupled to a network processor.

9. A method of framing data, comprising:

processing raw data within a pipeline of a plurality of stages to form framed data;

storing context data related to each stage of the plurality of stages within a memory; and

controlling interaction between the memory and the plurality of stages responsive to passage of data through the stages.

10. The method of claim 9 , further comprising:

receiving raw data from a link layer interface.

11. The method of claim 9 , further comprising:

providing framed data to a line interface.

12. The method of claim 9 , wherein:

the stages include a header insert stage, a CRC computation stage, a byte stuffing stage, and a data alignment stage.

13. The method of claim 12 , wherein

the stages further include a scrambling stage.

14. The method of claim 13 , wherein

the stages further include an arbitration stage.

15. The method of claim 14 , wherein

each stage of the plurality of stages processes data within the same predetermined number of clock cycles.

16. A method of deframing data, comprising:

processing framed data within a pipeline of a plurality of stages to form unframed data;

storing context data related to each stage of the plurality of stages within a memory; and

controlling interaction between the memory and the plurality of stages responsive to passage of data through the stages.

17. The method of claim 16 , further comprising:

receiving framed data from a line interface.

18. The method of claim 16 , further comprising:

providing unframed data to a link layer interface.

19. The method of claim 16 , wherein:

the stages include a synchronizer stage, a packet separator stage, a CRC checker stage, a byte destuffing stage, and a data alignment stage.

20. The method of claim 19 , wherein:

the stages further include a descrambling stage.

21. The method of claim 16 , further comprising:

receiving framed data from a line interface;

providing unframed data to a link layer interface;

and wherein:

the stages include a descrambling stage, a synchronizer stage, a packet separator, a CRC checker stage, a byte destuffing stage, and a data alignment stage.

22. The method of claim 21 , wherein:

each stage of the plurality of stages processes data within the same predetermined number of clock cycles.

23. A framer, comprising:

a pipeline formed of a plurality of means for processing data, the pipeline to process raw data to form framed data;

means for storing context data related to each stage of the plurality of stages within a memory; and

means for controlling interaction between the memory and the plurality of means for processing responsive to passage of data through the means for processing.

24. The framer of claim 23 , further comprising:

means for receiving raw data from a first external component.

25. The framer of claim 23 , further comprising:

means for providing framed data to a second external component.

26. The framer of claim 23 , wherein

the plurality of means for processing data include a means for synchronizing, a means for separating packets, a means for checking a CRC, a means for destuffing bytes, and a means for aligning data.