First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access
View Patent ↗Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.
1. A data assembler, comprising:
a first-in-first-out (FIFO) memory having a width of one unit;
a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read; and
a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write, wherein the read pointer is configured to increment by the unit access per read when the write pointer is configured to increment by the fraction of the unit access per write, wherein the read pointer is configured to increment by the fraction of the unit access per read when the write pointer is configured to increment by the unit access per write, wherein the read pointer is configured to increment by a number of bytes read from the FIFO memory, and wherein the write pointer is configured to increment by a number of bytes written in the FIFO memory.
2. The data assembler of claim 1 , wherein the FIFO memory is configured to receive data in variable-size packet fragments and output the data in fixed-size packet fragments by incrementing the read pointer by the unit access per read and the write pointer by the fraction of the unit access per write.
3. The data assembler of claim 2 , wherein the fraction of the unit access per write is equal to the number of bytes of the variable-size packet fragments written in the FIFO memory and the unit access per read is equal to an output data path width of the FIFO memory.
4. The data assembler of claim 3 , wherein the read pointer has a maximum value equal to a capacity of the FIFO memory divided by the output data path width of the FIFO memory.
5. The data assembler of claim 1 , wherein the FIFO memory is configured to receive data in fixed-size packet fragments and output the data in variable-size packet fragments by incrementing the write pointer by the unit access per write and the read pointer by the fraction of the unit access per read.
6. The data assembler of claim 5 , wherein the fraction of the unit access per read is equal to the number of bytes of the variable-size packet fragments read from the FIFO memory and the unit access per write is equal to an input data path width of the FIFO memory.
7. The data assembler of claim 6 , wherein the write pointer has a maximum value equal to a capacity of the FIFO memory divided by the input data path width of the FIFO memory.
8. The data assembler of claim 1 , further comprising a data extraction block coupled to the FIFO memory.
9. The data assembler of claim 1 , wherein the write pointer has a resolution of less than a data word width and the read pointer has a resolution of the data word width.
10. The data assembler of claim 1 , wherein the write pointer has a resolution of a data word width and the read pointer has a resolution of less than the data word width.
11. The data assembler of claim 1 , wherein the write pointer has a resolution of at least one of less than and equal to a data word width and the read pointer has a resolution of at least one of less than and equal to the data word width.
12. A method, comprising:
performing at least one of writing variable-size data packet fragments in a first-in-first-out (FIFO) memory and writing fixed-size data packet fragments in the FIFO memory;
incrementing a write pointer by a number of bytes written in the FIFO memory;
performing at least one of reading variable-size data packet fragments from the FIFO memory and reading fixed-size data packet fragments from the FIFO memory; and
incrementing a read pointer by a number of bytes read from the FIFO memory, wherein the read pointer is configured to increment by the unit access per read when the write pointer is configured to increment by the fraction of the unit access per write, wherein the read pointer is configured to increment by the fraction of the unit access per read when the write pointer is configured to increment by the unit access per write.
13. The method of claim 12 , wherein the write pointer increments by a fraction of a unit access per write if variable-size data packet fragments are written in the FIFO memory.
14. The method of claim 13 , wherein the unit access per write is equal to the output data path width of the FIFO memory.
15. The method of claim 13 , wherein the read pointer has a maximum value equal to a capacity of the FIFO memory divided by the output data path width of the FIFO memory.
16. The method of claim 12 , wherein the read pointer increments by a fraction of a unit access per read if fixed-size data packet fragments are written in the FIFO memory.
17. The method of claim 16 , wherein the unit access per read is equal to an input data path width of the FIFO memory.
18. The method of claim 16 , wherein the write pointer has a maximum value equal to a capacity of the FIFO memory divided by the input data path width of the FIFO memory.